VLSI Design, Automation and Test(VLSI-DAT)最新文献

{"title":"Case study of process and design performance debugging with Digital Speed Sensor","authors":"Chao-Wen Tzeng, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao","doi":"10.1109/VLSI-DAT.2015.7114548","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114548","url":null,"abstract":"Using speed sensor to find out the unexpected process variation and design performance degradation is getting more and more attention. In this paper, we demonstrate the industrial case of identifying process variation, with the power of in-house developed DSS (Digital Speed Sensor). The identification result is validated by TEM (Transmission Electron Microscopy). In addition, by using DSS, we can observe how the test environment results in design performance degradation, not only during the CP (Circuit Probe) test but also the board-level test.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122899997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A latency-elastic and fault-tolerant cache for improving performance and reliability on low voltage operation","authors":"Yung-Hui Yu, Po-Hao Wang, S. Tsai, Tien-Fu Chen","doi":"10.1109/VLSI-DAT.2015.7114576","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114576","url":null,"abstract":"The ever-increasing transistor threshold-voltage (Vth) variation caused by process technologies shrink brings the performance and reliability issues in SRAM cells. To keep power limitations, scaling down the supply voltage is inevitable in mobile devices and future chips. However, caches become susceptible even fail in low voltages, and the distribution of access latencies increases in new technology nodes. To deal with the respectable power of SRAM in modern processors, the memory reliability wall poses a major challenge in cache design nowadays and continues for years to come. This thesis proposes a latency-elastic and fault-tolerant cache not only for fault-tolerant, but aiming at the performance issues. It varies the latency of cache access to achieve better-than-worst-case designs for improving performance.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124787232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A wireless power transmission subsystem with capacitor-less high PSR LDO and thermal protection mechanism for artificial retina application","authors":"Yen-Fu Chen, K. Tang","doi":"10.1109/VLSI-DAT.2015.7114516","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114516","url":null,"abstract":"This paper presents a wireless power transmission subsystem with high power supply rejection (PSR) low dropout (LDO) regulator and thermal protection mechanism for artificial retina application. The proposed subsystem performs the functions of rectification, regulation and thermal detection. It can provide a stable DC source for implanted devices, and the subsystem only needs a small rectification capacitor. The proposed LDO achieves high PSRR performance of 46 dB at 10 MHz without any external capacitor. Moreover, the system contains the thermal protection mechanism to prevent cells from being damaged. A power controller in the system controls the received power by adjusting resonant capacitance in feedback. By controlling the received power, the system avoids receiving excessive power, enhances the power transmission efficiency, and avoids the device to be damaged by excessive heat. The proposed subsystem is to be fabricated with the TSMC 0.18 um CMOS process and occupies area of 556 um × 700 um. It achieves a high power conversion efficiency of 73 % under output voltage of 3.3 V and load current of 5 mA.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128735665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hydrogel-based microdevices","authors":"Y. Yang","doi":"10.1109/VLSI-DAT.2015.7114543","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114543","url":null,"abstract":"Summary form only given. This talk presents two hydrogel-based devices: a microgripper that can be wirelessly manipulated using magnetic fields, and a passive inertial switch using MWCNT-hydrogel composite integrated with an inductor/capacitor (L-C) resonator. The proposed microgripper can move freely in liquids when driven by direct current (dc) magnetic fields, and perform a gripping motion by using alternating current (ac) magnetic fields. The device is fabricated from a biocompatible hydrogel material that can be employed for intravascular applications. The actuation mechanism for gripping motions is realized by controlling the exposure dose on the hydrogel composite during the lithography process. The preliminary characterization of the device is also presented. The measurement results show that the gripping motion reached a full stroke at approximately 38 oC. By dispersing multiwall carbon nanotubes (MWCNT) into the material, the overall response time of the gripping motion decreases by approximately 2-fold. Device manipulations such as the gripping motion, translational motion, and rotational motion are also successfully demonstrated on a polyvinyl chloride (PVC) tube and in a polydimethylsiloxane (PDMS) microfluidic channel. The passive inertial switch consists of a PDMS micro-fluidic chip containing MWCNT-hydrogel composite and water droplet, and a glass substrate with a capacitor plate and an inductor coil. When the acceleration exceeds the designed threshold-level, the water passes through the channel to the hydrogel cavity. The hydrogel swells and changes the capacitance of the integrated L-C resonator, which in turn changes the resonant frequency that can be remotely detected. Each sensor unit does not require on-board power and circuitry for operation, so the proposed device is disposable, and is suitable for low-cost applications. All PDMS structures were fabricated using soft lithography. The L-C resonator was fabricated using a lift-off process to pattern metal layers on a glass substrate. The threshold g-values, which differ for various applications, were strongly affected by the channel widths. The phase-dip measurement shows that the resonant frequencies shift from 164 MHz to approximately 148 MHz when the device is activated by acceleration.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125276120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A pliable and batteryless real-time ECG monitoring system-in-a-patch","authors":"C. Wu, W. Kuo, H.-J. Wang, Y. Huang, Y.-H. Chen, Y.-Y. Chou, Sakurai Yu, Shey-Shi Lu","doi":"10.1109/VLSI-DAT.2015.7114521","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114521","url":null,"abstract":"A batteryless wearable ECG monitoring system-in-a-patch assembled by a biocompatible and pliable silicon-in-parylene technology is introduced. The system is capable of processing the acquired ECG signal and detecting arrhythmia by a built-in digital signal processor (DSP). An NFC communication system is used to interface the external reader. The silicon also integrates a sub-threshold ultra-low-voltage (ULV) boost converter to harvest body heat energy from a thermoelectric generator (TEG) attached to the chest to power up the ECG system. The boost converter operates with no external kick-off circuitry, and the average efficiency is up to 60%. The assembled all-in-one system achieves a very low profile (<;0.9mm); it includes one CMOS die, two SMD inductors (for the boost converter), and two in-parylene gold coils (for the NFC communication system). The pliable parylene mold provides excellent adhesion and skin comfort.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127097536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 2.5 mW/ch, 50 Mcps, 10-analog channel, adaptively biased read-out front-end IC with 9.71 ps-RMS timing resolution for single-photon time-of-flight PET applications in 90 nm CMOS","authors":"H. Cruz, Hong-Yi Huang, Shueen-Yu Lee, C. Luo","doi":"10.1109/VLSI-DAT.2015.7114501","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114501","url":null,"abstract":"A 10-channel time-of-flight (TOF) positron emission tomography (PET) IC that uses a digital-to-analog (DAC) - based architecture is implemented in 90nm CMOS process. The DAC is used to compensate for timing resolution variation attributed to amplifier gain fluctuation. Mixed-signal reset signals enhance photon counting speed achieving 5M counts/s/ch. The IC uses adaptive biases to stabilize the gain of preamplifiers and comparators. Multi-stage preamplifiers and comparator architectures were selected for low power. Measurement results show that these techniques enable the IC to achieve 9.71ps-RMS of intrinsic jitter and 181.5ps-FWHM (Full-width-at-half-maximum) timing resolution using an avalanche photo-diode and laser setup while consuming 2.5mW at 0.5V and 1.2V power supplies. The IC was fabricated in a 90nm CMOS process with area of 3.3 × 2.7mm2.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126760303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 84.7-DR wide BW incremental ADC using CT structure","authors":"Ting-Yang Wang, Tai-Cheng Lee","doi":"10.1109/VLSI-DAT.2015.7114519","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114519","url":null,"abstract":"This work uses continuous-tome (CT) structure to make the sigma-delta modulator faster and consuming less power. A third-order 3-bit CT-IDC with OSR=64 fabricated in TSMC T18 1P6M technology is proposed in the paper. The modulator is operated at 100MHz sampling clock. It achieves dynamic range of 84.7 dB, peak SNDR of 73.82 dB within the 737-kHz bandwidth. This chip dissipates 6.6mA from a 3.3V supply. The core area of this modulator occupies smaller than 0.25mm2.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123037310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Tunable and reconfigurable solutions using RFSOI-on-HR-Si technologies","authors":"J. Costa","doi":"10.1109/VLSI-DAT.2015.7114559","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114559","url":null,"abstract":"Summary form only given. Tunable and Reconfigurable applications using RFSOI-on-HR (high resistivity) silicon technology are being deployed in increasing numbers in today's advanced RF cellular handsets in order to provide increasing data rates demanded by the consumer market. These RFSOI solutions are being deployed to meet the demanding specifications of complex 4G RF cellular front-ends with numerous transmit and receive bands, as well as the possibility of multiple antennae and new architectures which involves Uplink and Downlink carrier aggregation. Such new architectures present extreme challenges for conventional fixed band systems composed of PA's, switches and filters. The talk will present a chronology of the RFSOI-on-HR silicon technology development in the industry through the last decade and highlight novel uses of its capabilities in 4G systems as well as the critical specifications needed in this application space.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130314535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Engineered substrates: The foundation to meet current and future RF requirements","authors":"Jean-Marc Le Meil, B. Aspar, E. Desbonnets, J. Raskin","doi":"10.1109/VLSI-DAT.2015.7114561","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114561","url":null,"abstract":"The increasing demand for wireless data bandwidth and the rapid adoption of LTE and LTE Advanced standards push radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance [1]. In this paper, Soitec and UCL explain the value of using RF-SOI substrates and more especially the new generation of Soitec widely adopted eSI™ (enhanced Signal Integrity) substrate to achieve the RF IC performance requested to address the LTE Advanced smart phone market.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133259320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The applications of power integrated circuits with energy saving","authors":"T. Liang","doi":"10.1109/VLSI-DAT.2015.7114541","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114541","url":null,"abstract":"Summary form only given. With the development of information technology, the power supplies for ITs' products have become more and more important. However, the power consumption and standby power losses for IT products such as data centers are increasing, which become a serious problem. Power electronics technologies are promising for energy saving. In this presentation, the market of power integrated circuits will be addressed first. The power losses on power adaptor with full load condition and light load condition are discussed. Finally, a high efficiency single-stage adaptor with primary control and quasi-resonant control is proposed. The experimental results are also provided to verify the performance of the proposed power integrated circuits.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121128025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}