A 84.7-DR wide BW incremental ADC using CT structure

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI:10.1109/VLSI-DAT.2015.7114519

Ting-Yang Wang, Tai-Cheng Lee

引用次数: 1

Abstract

This work uses continuous-tome (CT) structure to make the sigma-delta modulator faster and consuming less power. A third-order 3-bit CT-IDC with OSR=64 fabricated in TSMC T18 1P6M technology is proposed in the paper. The modulator is operated at 100MHz sampling clock. It achieves dynamic range of 84.7 dB, peak SNDR of 73.82 dB within the 737-kHz bandwidth. This chip dissipates 6.6mA from a 3.3V supply. The core area of this modulator occupies smaller than 0.25mm2.

查看原文本刊更多论文

这项工作采用连续体(CT)结构，使sigma-delta调制器速度更快，功耗更低。本文提出了一种采用TSMC T18 1P6M技术制造的OSR=64的三阶3位CT-IDC。调制器工作在100MHz采样时钟下。在737-kHz带宽范围内，动态范围为84.7 dB，峰值SNDR为73.82 dB。该芯片从3.3V电源耗散6.6mA。该调制器的核心面积小于0.25mm2。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

VLSI Design, Automation and Test(VLSI-DAT)

自引率

0.00%

发文量