Reusable and flexible verification methodology from architecture to RTL design

Abstract

This work presents our verification methodology from architecture to RTL design. There are three major benefits of the proposed verification methodology. First, this methodology enables the verification task to start at architecture design stage even without the implementation details. Second, the verification framework is well-organized and suitable for fully automation. Hence, human-introduced errors can be eliminated and the verification environment can be brought up efficiently. Thus verification engineers can focus on developing scenario to verify the RTL design. The most important one is that this methodology defines a framework for verifying designs at different design stages. In addition, flexibility is also kept for successive refinement of testbench when design state move from architecture to RTL stage. High reusability saves many manual efforts from developing and maintaining different verification environments for different design state. High flexibility makes the verification environment to be easily extended for different design stages.