VLSI Design, Automation and Test(VLSI-DAT)最新文献_第7页

Energy-harvesting microsystems 能量采集微系统公司

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI: 10.1109/VLSI-DAT.2015.7114540

G. Rincón-Mora

引用次数: 0

Variability-aware parametric yield enhancement via post-silicon tuning of hybrid redundant MAC units 基于混合冗余MAC单元后硅调谐的变量感知参数良率增强

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI: 10.1109/VLSI-DAT.2015.7114535

Sunil Dutt, Anshu Chauhan, Sukumar Nandi, G. Trivedi

引用次数: 0

The applications of power integrated circuits with energy saving 具有节能功能的电源集成电路的应用

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI: 10.1109/VLSI-DAT.2015.7114541

T. Liang

引用次数: 0

Improve transition fault diagnosability via observation point insertion 通过观测点插入提高过渡故障的可诊断性

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI: 10.1109/VLSI-DAT.2015.7114571

Cheng-Hung Wu, Yi-Da Wang, Kuen-Jong Lee

{"title":"Improve transition fault diagnosability via observation point insertion","authors":"Cheng-Hung Wu, Yi-Da Wang, Kuen-Jong Lee","doi":"10.1109/VLSI-DAT.2015.7114571","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114571","url":null,"abstract":"In this work, a design for diagnosability (DFD) method based on observation point (OP) insertion is proposed to improve the diagnosis resolution of transition faults in a circuit. The main objective is to minimize the number of observation points since this number will directly affect the area overhead of the circuit. We develop a novel algorithm to generate a set of OP candidates and then select a minimal number of OPs from this set which can distinguish all targeted fault pairs. An observation point insertion logic is also proposed that can efficiently reuse the output pins in the original circuit so as to reduce the number of extra output pins. In addition, a novel structural distance calculation method for synthesized circuits is proposed that considers the mixed structure of primitive gates and complicated gates, including AOI or OAI gates. Experimental results show that after applying the OP insertion method, all aborted fault pairs can be distinguished and the number of required observation points is quite small. We also use the observation points to distinguish those indistinguished far-away fault pairs. Experimental results show that all targeted fault pairs can be distinguished with a few observation points and a set of diagnosis patterns for ISCAS89 and ITC99 circuits.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"273 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124423209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

An energy-efficient resilient flip-flop circuit with built-in timing-error detection and correction 一种具有内置时间误差检测和校正的节能弹性触发器电路

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI: 10.1109/VLSI-DAT.2015.7114574

Che-Min Huang, Tsung-Te Liu, T. Chiueh

引用次数: 16

Active ESD protection for input transistors in a 40-nm CMOS process 40纳米CMOS工艺中输入晶体管的有源ESD保护

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI: 10.1109/VLSI-DAT.2015.7114533

F. Altolaguirre, M. Ker

引用次数: 4

An embedded ReRAM using a small-offset sense amplifier for low-voltage operations 一种嵌入式ReRAM，采用用于低压操作的小偏移感测放大器

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI: 10.1109/VLSI-DAT.2015.7114532

Albert Lee, Chien-Chen Lin, T. Yang, Meng-Fan Chang

引用次数: 4

Evaluation methods of computer memory system 计算机存储系统评价方法

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI: 10.1109/VLSI-DAT.2015.7114551

Shih-Lien Lu

引用次数: 0

Identify problematic layout patterns through volume diagnosis 通过体积诊断识别有问题的布局模式

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI: 10.1109/VLSI-DAT.2015.7114566

Wu-Tung Cheng

{"title":"Identify problematic layout patterns through volume diagnosis","authors":"Wu-Tung Cheng","doi":"10.1109/VLSI-DAT.2015.7114566","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114566","url":null,"abstract":"Summary form only given. Due to various manufacture difficulties in nano-scale semiconductor devices, certain layout patterns cannot be manufactured properly and cause significant yield loss. Due to the time to run through complete lithography simulation, it is impossible to identify all of them before silicon manufacture. Therefore, post-silicon physical failure analysis is needed to find them one-by-one to improve yield iteratively with each re-spin. However, physical failure analysis is time-consuming such that each re-spin can take a long time. To speed-up yield ramp-up, we proposed to automatically identify as many layout patterns as possible by using volume diagnosis from post-silicon manufacture failure data. Typically volume diagnosis uses two procedures. First, responses from failing devices are analyzed using defect diagnosis tools. Next the results of diagnoses are analyzed using statistical, data mining and machine learning techniques to effectively determine the underlying problematic layout patterns. In this presentation, we will discuss the procedures and statistics methods for analyzing diagnosis data and put special attention to the link between defects and layout patterns.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134404638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Power and sensor semiconductors driving automotive applications 驱动汽车应用的功率和传感器半导体

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI: 10.1109/VLSI-DAT.2015.7114552

H. Stork

引用次数: 0