VLSI Design, Automation and Test(VLSI-DAT)最新文献_第4页

Clock-domain-aware test for improving pattern compression 改进模式压缩的时钟域感知测试

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI: 10.1109/VLSI-DAT.2015.7114506

Kun-Han Tsai, J. Rajski

引用次数: 2

Design and VLSI implementation of novel pre-screening and simplified sorting based K-best detection for MIMO systems MIMO系统基于K-best检测的新型预筛选和简化排序的设计和VLSI实现

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI: 10.1109/VLSI-DAT.2015.7114511

Jheng-Jhan He, Chih-Peng Fan

引用次数: 1

A high-PSRR ADPLL with self-regulated GRO TDC and DCO-dedicated voltage regulator 具有自调节GRO TDC和dco专用稳压器的高psrr ADPLL

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI: 10.1109/VLSI-DAT.2015.7114499

Yanfeng Li, Yutao Liu, W. Rhee, Zhihua Wang

引用次数: 0

Drivers and aspects of 2.5/3D integration as a potential game-changer 2.5/3D集成的驱动因素和方面可能会改变游戏规则

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI: 10.1109/VLSI-DAT.2015.7114555

Carl Engblom

引用次数: 0

System-level test coverage prediction by structural stress test data mining 基于结构应力测试数据挖掘的系统级测试覆盖率预测

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI: 10.1109/VLSI-DAT.2015.7114508

Bing-Yang Lin, Cheng-Wen Wu, Harry H. Chen

{"title":"System-level test coverage prediction by structural stress test data mining","authors":"Bing-Yang Lin, Cheng-Wen Wu, Harry H. Chen","doi":"10.1109/VLSI-DAT.2015.7114508","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114508","url":null,"abstract":"To achieve high quality of silicon ICs, system-level test (SLT) can be performed after regular final test. This is important for chips manufactured in advanced technologies, as systematic failures are getting harder to detect by conventional structural tests. However, due to long test time and extra human efforts, the cost for SLT is high. A possible way to replace SLT without quality loss is to identify SLT failure suspects with stress tests. In this work, we apply 60,000 structural stress test patterns to the CPU blocks of a real SOC product, using 20 stressed voltage-frequency corners. We try to identify the correlation between the stress test data and SLT-pass/fail results of the CPU blocks. By the proposed differential feature-based methodology, 32 outliers are identified, which are assumed to be CPU-fail chips. Because of the lack of exact CPU-fail chip IDs for verification, the identified chip IDs are compared with the IDs identified from previous works, which use the same data but different machine-learning features and method for the same purpose. After comparison, 30 out of a total of 33 CPU-fail suspects matched. Although this does not immediately imply that the SLT can be replaced by the structural stress tests, it shows more evidence that test data mining can be further explored for test time reduction and/or quality improvement.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130859455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Energy efficient design and energy harvesting for energy autonomous systems 能源自主系统的节能设计和能量收集

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI: 10.1109/VLSI-DAT.2015.7114542

M. Takamiya

引用次数: 9

An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support 一个OpenGL ES 2.0 3D图形SoC与通用的硬件/软件开发支持

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI: 10.1109/VLSI-DAT.2015.7114496

Hsu-Kang Dow, Ching-Hua Huang, Chun-Hung Lai, K. Tsao, Sheng-Chih Tseng, Kun-Yi Wu, Ting-Hsuan Wu, Ho-Chun Yang, Da-Jing Zhang-Jian, Yun-Nan Chang, S.W. Haga, Shen-Fu Hsiao, Ing-Jer Huang, Shiann-Rong Kuang, Chung-Nan Lee

引用次数: 3

SoC test integration platform SoC测试集成平台

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI: 10.1109/VLSI-DAT.2015.7114546

A. Kifli, Kun-Cheng Wu

引用次数: 1

An effective matrix compression method for GPU-accelerated thermal analysis 一种用于gpu加速热分析的有效矩阵压缩方法

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI: 10.1109/VLSI-DAT.2015.7114505

L. Chiou, L. Lu, Chieh-Yu Lin

引用次数: 0

A time delay integration CMOS image sensor with online deblurring algorithm 一种带有在线去模糊算法的延时集成CMOS图像传感器

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI: 10.1109/VLSI-DAT.2015.7114510

Hang Yu, Xinyuan Qian, M. Guo, Shoushun Chen, K. Low

引用次数: 2