改进模式压缩的时钟域感知测试

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI:10.1109/VLSI-DAT.2015.7114506

Kun-Han Tsai, J. Rajski

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引用次数: 2

摘要

提出了一种DFT与ATPG相结合的方法，以提高脉冲交互时钟(PIC)的模式压缩性能。该算法可以准确地屏蔽任意时钟偏差下的不可靠的跨时钟域跃迁。此外，它还可以识别需要插入的flops保持路径，并与ATPG结合使用，在不影响测试质量的情况下将模式计数减少39%。

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Clock-domain-aware test for improving pattern compression

This paper proposes an integration method between DFT and ATPG to improve the pattern compression by pulsing interactive clocks (PIC) simultaneously. The proposed algorithm can accurately mask the unreliable cross clock domain transitions for any clock skews. In addition, it identifies the required flops to be inserted hold paths, and combined with ATPG to reduce the pattern count by up to 39% without compromising the test quality.

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VLSI Design, Automation and Test(VLSI-DAT)

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