A high-PSRR ADPLL with self-regulated GRO TDC and DCO-dedicated voltage regulator

Abstract

This paper describes a PSRR enhancing method for the all-digital phase-locked loop (ADPLL) by utilizing a self-regulated gated ring-oscillator (SR-GRO) time-to-digital converter (TDC) and a voltage regulator just for a digitally-controlled oscillator (DCO). The SR-GRO employs a replica supply noise monitoring circuit which tracks supply noise and enables feed-forward error cancellation over broad spectrum. A prototype ADPLL implemented in 65nm CMOS achieves >25dB PSRR when 100mVpp 1MHz supply noise is injected to both the TDC and the DCO. Experimental results show that the SR-GRO TDC can also suppress the supply coupling induced phase noise.