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37th International Symposium on Multiple-Valued Logic (ISMVL'07)最新文献

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Restriction-Closed Hyperclones Restriction-Closed Hyperclones
37th International Symposium on Multiple-Valued Logic (ISMVL'07) Pub Date : 2007-05-13 DOI: 10.1109/ISMVL.2007.50
B. A. Romov
{"title":"Restriction-Closed Hyperclones","authors":"B. A. Romov","doi":"10.1109/ISMVL.2007.50","DOIUrl":"https://doi.org/10.1109/ISMVL.2007.50","url":null,"abstract":"The sets of multi-valued operations closed with respect to compositions and restrictions, called restriction- closed hyperclones, defined on the finite set E(k)={0, 1,..., k-1} (kges2) are investigated. The set of all maximal restriction-closed pre-hyperclones (composition without projections) is obtained. Based on it the analogue of Slupecki completeness criteria in restriction-closed pre-hyperclones is established. Next the problem of classification of restriction-closed hyperclones according to their single-valued clone component is considered.","PeriodicalId":368339,"journal":{"name":"37th International Symposium on Multiple-Valued Logic (ISMVL'07)","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124892742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction 基于有源负载双轨差分逻辑的高性能多值比较器串扰降噪
37th International Symposium on Multiple-Valued Logic (ISMVL'07) Pub Date : 2007-05-13 DOI: 10.1109/ISMVL.2007.28
A. Mochizuki, M. Miura, T. Hanyu
{"title":"High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction","authors":"A. Mochizuki, M. Miura, T. Hanyu","doi":"10.1109/ISMVL.2007.28","DOIUrl":"https://doi.org/10.1109/ISMVL.2007.28","url":null,"abstract":"new multiple-valued comparator based on active-load dual-rail differential logic is proposed for crosstalk-noise reduction while maintaining the switching speed. The use of dual-rail complementary differential-pair circuits (DPCs) whose outputs are summed up each other by wiring makes the common-mode noise reduced, yet the switching speed enhanced. By using the diode-connected cross-coupled PMOS active loads, the rapid transition behaviors in the DPC is relaxed appropriately, which can also eliminate a spike-shaped input noise. It is demonstrated in 0.18 mum CMOS that the noise-reduction ratio and the switching delay of the proposed comparator is superior to those of a corresponding previous one.","PeriodicalId":368339,"journal":{"name":"37th International Symposium on Multiple-Valued Logic (ISMVL'07)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115553621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Experimental Studies on SAT-Based ATPG for Gate Delay Faults 基于sat的门延迟故障ATPG实验研究
37th International Symposium on Multiple-Valued Logic (ISMVL'07) Pub Date : 2007-05-13 DOI: 10.1109/ISMVL.2007.21
Stephan Eggersglüß, Daniel Tille, G. Fey, R. Drechsler, Andreas Glowatz, F. Hapke, J. Schlöffel
{"title":"Experimental Studies on SAT-Based ATPG for Gate Delay Faults","authors":"Stephan Eggersglüß, Daniel Tille, G. Fey, R. Drechsler, Andreas Glowatz, F. Hapke, J. Schlöffel","doi":"10.1109/ISMVL.2007.21","DOIUrl":"https://doi.org/10.1109/ISMVL.2007.21","url":null,"abstract":"The clock rate of modern chips is still increasing and at the same time the gate size decreases. As a result, already slight variations during the production process may cause a functional failure. Therefore, dynamic fault models like the gate delay fault model are becoming more important. Meanwhile classical algorithms for test pattern generation reach their limits regarding run time and memory needs. In this work, a SAT-based approach to calculate test patterns for gate delay faults is presented. The basic transformation is explained in detail. The application to industrial circuits - where multi-valued logic has to be considered - is studied and experimental results are reported.","PeriodicalId":368339,"journal":{"name":"37th International Symposium on Multiple-Valued Logic (ISMVL'07)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123508482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Quantum Robots for Teenagers 面向青少年的量子机器人
37th International Symposium on Multiple-Valued Logic (ISMVL'07) Pub Date : 2007-05-13 DOI: 10.1109/ISMVL.2007.46
Arushi Raghuvanshi, Yale Fan, Michal Woyke, M. Perkowski
{"title":"Quantum Robots for Teenagers","authors":"Arushi Raghuvanshi, Yale Fan, Michal Woyke, M. Perkowski","doi":"10.1109/ISMVL.2007.46","DOIUrl":"https://doi.org/10.1109/ISMVL.2007.46","url":null,"abstract":"Extending the ideas of quantum Braitenberg vehicles from (A. Raghuvanshi, 2006), we present here a family of Lego robots controlled by multiple-valued quantum circuits. The robots have at most 6 degrees of freedom (motors) and 6 sensors. Their basic architecture is a generalization of robots from (Ch. Brawn et al, 2006) to more versatile multiple-valued quantum automata (simulated in software). We believe that building robots with \"quantum brains\" is an excellent future application of quantum computing and now it helps students to learn principles of quantum circuits. We present a one-year project in \"quantum robotics for teenagers\". Our project brings research and educational perspectives, which are both presented in this paper.","PeriodicalId":368339,"journal":{"name":"37th International Symposium on Multiple-Valued Logic (ISMVL'07)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114756801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Dual Data-Rate Cyclic D/A Converter Using Semi Floating-Gate Devices 采用半浮门器件的双数据速率循环数模转换器
37th International Symposium on Multiple-Valued Logic (ISMVL'07) Pub Date : 2007-05-13 DOI: 10.1109/ISMVL.2007.15
R. Jensen, Y. Berg
{"title":"Dual Data-Rate Cyclic D/A Converter Using Semi Floating-Gate Devices","authors":"R. Jensen, Y. Berg","doi":"10.1109/ISMVL.2007.15","DOIUrl":"https://doi.org/10.1109/ISMVL.2007.15","url":null,"abstract":"This paper focuses on compact and configurable multiple-valued (MV) encoders. For this purpose, a new cyclic D/A converter circuit using semi floating-gate (SFG) inverters is proposed. Slow conversion rates are considered a problem in cyclic D/A converters. A new algorithm called Dual Data Rate (DDR) mode of operation is introduced allowing two iterations per clock cycle instead of only one when using SFG inverters. The proposed converter is implemented in a double poly 0.35 mum process. Experimental results are provided for radix 4, 8 and 16. Operation of both clock edges using DDR mode of operation is demonstrated. This gives a significant improvement in terms of conversion rate and noise-margins.","PeriodicalId":368339,"journal":{"name":"37th International Symposium on Multiple-Valued Logic (ISMVL'07)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114783333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Characterization of Partial Sheffer Functions in 3-Valued Logic 3值逻辑中部分Sheffer函数的表征
37th International Symposium on Multiple-Valued Logic (ISMVL'07) Pub Date : 2007-05-13 DOI: 10.1109/ISMVL.2007.12
L. Haddad, D. Lau
{"title":"Characterization of Partial Sheffer Functions in 3-Valued Logic","authors":"L. Haddad, D. Lau","doi":"10.1109/ISMVL.2007.12","DOIUrl":"https://doi.org/10.1109/ISMVL.2007.12","url":null,"abstract":"partial function f on a k-element set k is a partial Sheffer function if every partial function on k is definable in terms of f. Since this holds if and only if f belongs to no maximal partial clone on k, a characterization of partial Sheffer functions reduces to finding families of minimal coverings of maximal partial clones on k. We present minimal coverings of maximal partial clones on k for k = 2 and k = 3 and deduce criteria for partial Sheffer functions on a 2-element and a 3-element set.","PeriodicalId":368339,"journal":{"name":"37th International Symposium on Multiple-Valued Logic (ISMVL'07)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114429687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An Application of 16-Valued Logic to Design of Reconfigurable Logic Arrays 16值逻辑在可重构逻辑阵列设计中的应用
37th International Symposium on Multiple-Valued Logic (ISMVL'07) Pub Date : 2007-05-13 DOI: 10.1109/ISMVL.2007.7
Tsutomu Sasao
{"title":"An Application of 16-Valued Logic to Design of Reconfigurable Logic Arrays","authors":"Tsutomu Sasao","doi":"10.1109/ISMVL.2007.7","DOIUrl":"https://doi.org/10.1109/ISMVL.2007.7","url":null,"abstract":"This paper presents a method to implement a reconfigurable logic array by using FPGA. 16-valued logic is introduced to design circuits with 2-valued 4-input LUTs. Symmetric functions and adders can be efficiently represented, as well as benchmark functions. Comparisons with 2-valued expressions and 4-valued expressions are done. Both sum-of-products expressions and EXOR sum-of-products expressions of 16-valued logic significantly reduces needed FPGA resources.","PeriodicalId":368339,"journal":{"name":"37th International Symposium on Multiple-Valued Logic (ISMVL'07)","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123523204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL SystemVerilog HDL中指定的MVL电路的开关覆盖评估
37th International Symposium on Multiple-Valued Logic (ISMVL'07) Pub Date : 2007-05-13 DOI: 10.1109/ISMVL.2007.19
Mahsan Amoui, Daniel Große, M. Thornton, R. Drechsler
{"title":"Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL","authors":"Mahsan Amoui, Daniel Große, M. Thornton, R. Drechsler","doi":"10.1109/ISMVL.2007.19","DOIUrl":"https://doi.org/10.1109/ISMVL.2007.19","url":null,"abstract":"Designing modern circuits comprised of millions of gates is a very challenging task. Therefore new directions are investigated for efficient modeling and verification of such systems. Recently, a new language, SystemVerilog, was introduced and became an IEEE standard. SystemVerilog extends the hardware description language Verilog by including higher abstraction levels and integrated verification features. In this paper, we first present the concept of modeling multiple valued logic circuits in SystemVerilog. We demonstrate that this approach allows for efficient simulation of complex multiple valued logic systems. Secondly, we show how SystemVerilog can be used to ensure functional correctness. A generalization of binary toggle coverage for the multiple valued logic domain is presented and evaluated. As a test case, a scalable multiple valued logic arithmetic unit is modeled and experimental results for multiple valued logic toggle coverage are given.","PeriodicalId":368339,"journal":{"name":"37th International Symposium on Multiple-Valued Logic (ISMVL'07)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121236095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC 在SystemC中基于GF(p^{m})的完全可伸缩Reed-Solomon编码器/解码器建模
37th International Symposium on Multiple-Valued Logic (ISMVL'07) Pub Date : 2007-05-13 DOI: 10.1109/ISMVL.2007.34
André Sülflow, R. Drechsler
{"title":"Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC","authors":"André Sülflow, R. Drechsler","doi":"10.1109/ISMVL.2007.34","DOIUrl":"https://doi.org/10.1109/ISMVL.2007.34","url":null,"abstract":"In this paper we describe how to model arithmetic circuits over GF(pm) in SystemC. An extension of a GF(2m) multiplier is presented to support GF(pm) arithmetic as well. A full integration in the simulation environment is discussed and the proposed solution can be fully synthesized down to hardware. This finds application in e.g. cryptographic systems. As a case study a Reed-Solomon encoder/decoder system was developed with full GF(pm) encoding/decoding capability. It is shown that the modeling of a HW/SW co-design system in SystemC can improve the speed of simulation by a factor of up to 17.","PeriodicalId":368339,"journal":{"name":"37th International Symposium on Multiple-Valued Logic (ISMVL'07)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115584820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Simulation of Gate Circuits with Feedback in Multi-Valued Algebras 多值代数中带反馈的门电路仿真
37th International Symposium on Multiple-Valued Logic (ISMVL'07) Pub Date : 2007-05-13 DOI: 10.1109/ISMVL.2007.51
J. Brzozowski, Yuli Ye
{"title":"Simulation of Gate Circuits with Feedback in Multi-Valued Algebras","authors":"J. Brzozowski, Yuli Ye","doi":"10.1109/ISMVL.2007.51","DOIUrl":"https://doi.org/10.1109/ISMVL.2007.51","url":null,"abstract":"Simulation of gate circuits is an efficient method of detecting hazards and oscillations that may occur because of delays. Ternary simulation consists of two algorithms, A andB, and is well understood. It has been generalized to an infinite algebra C and finite algebras Ckappa, k ges 2, where Ci is ternary algebra. Simulation in C has been studied extensively for feedback-free circuits, for which algorithm A always terminates and algorithm B is unnecessary. We study the simulation of gate circuits with feedback infinite algebras Ckappa- The gate functions are restricted to a set that includes all the 1- and 2-variable functions and multi-input AND, OR, NAND, NOR, XOR and XNOR functions. We prove that Algorithm B in Algebra Ckappa, for k > 2, provides no more information than in ternary algebra. Thus, for any gate in any circuit, the final result of Algorithm B is always one of the binary values, 0 or 1, or the \"uncertain\" value; the remaining values of Ckappa never appear. This permits us to replace Algorithm B in Ckappa by the same algorithm in ternary algebra, and to reduce the simulation time.","PeriodicalId":368339,"journal":{"name":"37th International Symposium on Multiple-Valued Logic (ISMVL'07)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124831876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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