{"title":"16值逻辑在可重构逻辑阵列设计中的应用","authors":"Tsutomu Sasao","doi":"10.1109/ISMVL.2007.7","DOIUrl":null,"url":null,"abstract":"This paper presents a method to implement a reconfigurable logic array by using FPGA. 16-valued logic is introduced to design circuits with 2-valued 4-input LUTs. Symmetric functions and adders can be efficiently represented, as well as benchmark functions. Comparisons with 2-valued expressions and 4-valued expressions are done. Both sum-of-products expressions and EXOR sum-of-products expressions of 16-valued logic significantly reduces needed FPGA resources.","PeriodicalId":368339,"journal":{"name":"37th International Symposium on Multiple-Valued Logic (ISMVL'07)","volume":"184 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"An Application of 16-Valued Logic to Design of Reconfigurable Logic Arrays\",\"authors\":\"Tsutomu Sasao\",\"doi\":\"10.1109/ISMVL.2007.7\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a method to implement a reconfigurable logic array by using FPGA. 16-valued logic is introduced to design circuits with 2-valued 4-input LUTs. Symmetric functions and adders can be efficiently represented, as well as benchmark functions. Comparisons with 2-valued expressions and 4-valued expressions are done. Both sum-of-products expressions and EXOR sum-of-products expressions of 16-valued logic significantly reduces needed FPGA resources.\",\"PeriodicalId\":368339,\"journal\":{\"name\":\"37th International Symposium on Multiple-Valued Logic (ISMVL'07)\",\"volume\":\"184 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-05-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"37th International Symposium on Multiple-Valued Logic (ISMVL'07)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.2007.7\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"37th International Symposium on Multiple-Valued Logic (ISMVL'07)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.2007.7","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An Application of 16-Valued Logic to Design of Reconfigurable Logic Arrays
This paper presents a method to implement a reconfigurable logic array by using FPGA. 16-valued logic is introduced to design circuits with 2-valued 4-input LUTs. Symmetric functions and adders can be efficiently represented, as well as benchmark functions. Comparisons with 2-valued expressions and 4-valued expressions are done. Both sum-of-products expressions and EXOR sum-of-products expressions of 16-valued logic significantly reduces needed FPGA resources.
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