High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction

Abstract

new multiple-valued comparator based on active-load dual-rail differential logic is proposed for crosstalk-noise reduction while maintaining the switching speed. The use of dual-rail complementary differential-pair circuits (DPCs) whose outputs are summed up each other by wiring makes the common-mode noise reduced, yet the switching speed enhanced. By using the diode-connected cross-coupled PMOS active loads, the rapid transition behaviors in the DPC is relaxed appropriately, which can also eliminate a spike-shaped input noise. It is demonstrated in 0.18 mum CMOS that the noise-reduction ratio and the switching delay of the proposed comparator is superior to those of a corresponding previous one.