基于sat的门延迟故障ATPG实验研究

Stephan Eggersglüß, Daniel Tille, G. Fey, R. Drechsler, Andreas Glowatz, F. Hapke, J. Schlöffel
{"title":"基于sat的门延迟故障ATPG实验研究","authors":"Stephan Eggersglüß, Daniel Tille, G. Fey, R. Drechsler, Andreas Glowatz, F. Hapke, J. Schlöffel","doi":"10.1109/ISMVL.2007.21","DOIUrl":null,"url":null,"abstract":"The clock rate of modern chips is still increasing and at the same time the gate size decreases. As a result, already slight variations during the production process may cause a functional failure. Therefore, dynamic fault models like the gate delay fault model are becoming more important. Meanwhile classical algorithms for test pattern generation reach their limits regarding run time and memory needs. In this work, a SAT-based approach to calculate test patterns for gate delay faults is presented. The basic transformation is explained in detail. The application to industrial circuits - where multi-valued logic has to be considered - is studied and experimental results are reported.","PeriodicalId":368339,"journal":{"name":"37th International Symposium on Multiple-Valued Logic (ISMVL'07)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Experimental Studies on SAT-Based ATPG for Gate Delay Faults\",\"authors\":\"Stephan Eggersglüß, Daniel Tille, G. Fey, R. Drechsler, Andreas Glowatz, F. Hapke, J. Schlöffel\",\"doi\":\"10.1109/ISMVL.2007.21\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The clock rate of modern chips is still increasing and at the same time the gate size decreases. As a result, already slight variations during the production process may cause a functional failure. Therefore, dynamic fault models like the gate delay fault model are becoming more important. Meanwhile classical algorithms for test pattern generation reach their limits regarding run time and memory needs. In this work, a SAT-based approach to calculate test patterns for gate delay faults is presented. The basic transformation is explained in detail. The application to industrial circuits - where multi-valued logic has to be considered - is studied and experimental results are reported.\",\"PeriodicalId\":368339,\"journal\":{\"name\":\"37th International Symposium on Multiple-Valued Logic (ISMVL'07)\",\"volume\":\"60 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-05-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"37th International Symposium on Multiple-Valued Logic (ISMVL'07)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.2007.21\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"37th International Symposium on Multiple-Valued Logic (ISMVL'07)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.2007.21","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10

摘要

现代芯片的时钟速率仍在不断提高,而栅极尺寸却在不断减小。因此,在生产过程中已经很小的变化可能会导致功能故障。因此,像门延迟故障模型这样的动态故障模型变得越来越重要。同时,经典的测试模式生成算法在运行时间和内存需求方面达到了极限。在这项工作中,提出了一种基于sat的门延迟故障测试模式计算方法。详细说明了基本的转换。研究了多值逻辑在工业电路中的应用,并给出了实验结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Experimental Studies on SAT-Based ATPG for Gate Delay Faults
The clock rate of modern chips is still increasing and at the same time the gate size decreases. As a result, already slight variations during the production process may cause a functional failure. Therefore, dynamic fault models like the gate delay fault model are becoming more important. Meanwhile classical algorithms for test pattern generation reach their limits regarding run time and memory needs. In this work, a SAT-based approach to calculate test patterns for gate delay faults is presented. The basic transformation is explained in detail. The application to industrial circuits - where multi-valued logic has to be considered - is studied and experimental results are reported.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信