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[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic最新文献

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Design of highly parallel residue arithmetic circuits based on multiple-valued bidirectional current-mode MOS technology 基于多值双向电流模MOS技术的高并行剩余运算电路设计
[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic Pub Date : 1988-05-24 DOI: 10.1109/ISMVL.1988.5142
M. Kameyama, T. Sekibe, T. Higuchi
{"title":"Design of highly parallel residue arithmetic circuits based on multiple-valued bidirectional current-mode MOS technology","authors":"M. Kameyama, T. Sekibe, T. Higuchi","doi":"10.1109/ISMVL.1988.5142","DOIUrl":"https://doi.org/10.1109/ISMVL.1988.5142","url":null,"abstract":"A residue arithmetic circuit based on multiple-valued bidirectional current-mode MOS technology is proposed. Each residue digit is represented by multiple-valued coding suitable for highly parallel computation. Using the coding, mod m/sub i/ multiplication can be simply performed by a shift operation. In mod m/sub i/ addition, radix-five signed-digit full adders are used to obtain a high degree of parallelism and multiple-operand addition, so that the high-speed arithmetic operation can be achieved. A novel parallel scaling algorithm is discussed. A mod-seven three-operand multiply-adder is designed for an integrated circuit based on 10- mu m CMOS technology.<<ETX>>","PeriodicalId":368020,"journal":{"name":"[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121388026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
The incremental-cost approach for synthesis of CCD 4-valued unary functions CCD四值一元函数合成的增量代价法
[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic Pub Date : 1988-05-24 DOI: 10.1109/ISMVL.1988.5154
M. Abd-El-Barr, T. Hoang, Z. Vranesic
{"title":"The incremental-cost approach for synthesis of CCD 4-valued unary functions","authors":"M. Abd-El-Barr, T. Hoang, Z. Vranesic","doi":"10.1109/ISMVL.1988.5154","DOIUrl":"https://doi.org/10.1109/ISMVL.1988.5154","url":null,"abstract":"A novel approach to the synthesis of one-variable four-valued functions using CCDs (charge-coupled devices) is presented. Starting at zero cost, a search is conducted for the possible functions that can be realized using basic CCD gate structures. These functions are recorded in a list. At a given cost C, each of the four possibilities of using the addition, overflow, inhibit, and multiplication as an output gate is considered. For each possibility, the set of possible inputs to the gate are determined and used. Only those outputs which are not covered at lower costs are added to the list. The cost is then incremented by one and the search is repeated for new functions. The process terminates when all 256 possible functions are in the list. Using this approach, it is shown that in 195 functions (76% of the total) there is a cost improvement compared to existing approaches.<<ETX>>","PeriodicalId":368020,"journal":{"name":"[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122610265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
On NPN logic 关于NPN逻辑
[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic Pub Date : 1988-05-24 DOI: 10.1109/ISMVL.1988.5199
W.-R. Zhang, S.-s. Chen, K.-H. Chen, M. Zhang, J. Bezdek
{"title":"On NPN logic","authors":"W.-R. Zhang, S.-s. Chen, K.-H. Chen, M. Zhang, J. Bezdek","doi":"10.1109/ISMVL.1988.5199","DOIUrl":"https://doi.org/10.1109/ISMVL.1988.5199","url":null,"abstract":"It is argued that two-valued logic and fuzzy logic both lack some representational and reasoning capability in modeling directly a social or natural world with a combination of positive, negative, and neutral relationships. This is due to the fact that the logic values in both lie in the interval (0, 1). An NPN (negative-positive-neutral) crisp logic and an NPN fuzzy logic are presented that assume, respectively, crisp or fuzzy values in the interval (-1, 1). The notions of NPN relations and NPN heuristic transitive closures are introduced. It is suggested that NPN logics can be embedded into NPN relations for cognitive process modeling. An application is given to illustrate the theory.<<ETX>>","PeriodicalId":368020,"journal":{"name":"[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128728872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
On the associativity of C(x, y) and x-C(x, 1-y) 关于C(x, y)与x-C(x, 1-y)的结合律
[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic Pub Date : 1988-05-24 DOI: 10.1109/ISMVL.1988.5148
C. Alsina, J. J. Quesada
{"title":"On the associativity of C(x, y) and x-C(x, 1-y)","authors":"C. Alsina, J. J. Quesada","doi":"10.1109/ISMVL.1988.5148","DOIUrl":"https://doi.org/10.1109/ISMVL.1988.5148","url":null,"abstract":"In the framework of generalized logical connectives the authors study the simultaneous associativity of the copulas C(x, y) and x-C(x, 1-y). The techniques of the theory of functional equations are used.<<ETX>>","PeriodicalId":368020,"journal":{"name":"[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114230354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A semi-custom technique realizing nondestructive information processing 一种实现无损信息处理的半定制技术
[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic Pub Date : 1988-05-24 DOI: 10.1109/ISMVL.1988.5147
W. Lin, Q. Zheng, G. Huang
{"title":"A semi-custom technique realizing nondestructive information processing","authors":"W. Lin, Q. Zheng, G. Huang","doi":"10.1109/ISMVL.1988.5147","DOIUrl":"https://doi.org/10.1109/ISMVL.1988.5147","url":null,"abstract":"A semicustom multiple-valued logic array integrated circuit (SCMAIC) that is able to realize nondestructive information processing is processed. It uses compatible NMOS-DYL multiple-valued logic circuits as basic units. Experimental studies indicate that it is impossible to integrate thousands of SCMAICs in a chip. The units can be used to fabricate gate arrays.<<ETX>>","PeriodicalId":368020,"journal":{"name":"[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124343688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A survey of some results in lattice-valued model theory 格值模型理论中一些结果的综述
[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic Pub Date : 1988-05-24 DOI: 10.1109/ISMVL.1988.5164
S. Wang
{"title":"A survey of some results in lattice-valued model theory","authors":"S. Wang","doi":"10.1109/ISMVL.1988.5164","DOIUrl":"https://doi.org/10.1109/ISMVL.1988.5164","url":null,"abstract":"The author surveys some of his published results on the model theory of lattice-valued logic. Among the results surveyed are: the fundamental theorem of ultraproducts, the compactness theorem, the LST theorem, and the omitting types theorem. A proof of the compactness theorem is appended.<<ETX>>","PeriodicalId":368020,"journal":{"name":"[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117174925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Directed search minimization of multiple-valued functions 多值函数的定向搜索最小化
[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic Pub Date : 1988-05-24 DOI: 10.1109/ISMVL.1988.5177
G. Dueck, D.M. Miller
{"title":"Directed search minimization of multiple-valued functions","authors":"G. Dueck, D.M. Miller","doi":"10.1109/ISMVL.1988.5177","DOIUrl":"https://doi.org/10.1109/ISMVL.1988.5177","url":null,"abstract":"A directed search algorithm to minimize multiple-valued input functions with a single binary output is presented. A multiple binary output minimization problem is readily transformed to such a function. Further, any multiple-valued function can be transformed to a multiple binary output problem and hence to a function suited to the presented algorithm. The proposed algorithm can thus be applied to a broad class of minimization problems. Heuristics suitable for PLA (programmable logic arrays) realizations are used. Some results showing the performance of the algorithm are presented.<<ETX>>","PeriodicalId":368020,"journal":{"name":"[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116717495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
An iterative characterization of post algebras 后代数的迭代表征
[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic Pub Date : 1988-05-24 DOI: 10.1109/ISMVL.1988.5163
C. Reischer, D. Simovici
{"title":"An iterative characterization of post algebras","authors":"C. Reischer, D. Simovici","doi":"10.1109/ISMVL.1988.5163","DOIUrl":"https://doi.org/10.1109/ISMVL.1988.5163","url":null,"abstract":"A previous iterative characterization of Boolean algebras is extended to Post algebras. Use is made of iterative properties of algebraic functions on certain algebras constructed on the underlying lattice of a Post algebra.<<ETX>>","PeriodicalId":368020,"journal":{"name":"[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117187176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Quaternary logic for carry-lookahead binary addition 进位二进制加法的四元逻辑
[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic Pub Date : 1988-05-24 DOI: 10.1109/ISMVL.1988.5186
M. A. Manzoul, A. Bommireddy
{"title":"Quaternary logic for carry-lookahead binary addition","authors":"M. A. Manzoul, A. Bommireddy","doi":"10.1109/ISMVL.1988.5186","DOIUrl":"https://doi.org/10.1109/ISMVL.1988.5186","url":null,"abstract":"The role of the quaternary (four-valued) logic in speeding up the binary addition is discussed. An improved carry-lookahead adder circuit, which is completely realizable by binary gates, is presented. The speed of the proposed n-bit adder is compared to the traditional carry-lookahead n-bit adder in terms of gate delays and fan-in. Results show that the proposed adder is faster in certain ranges determined by n. For an 8-bit adder, the circuit can save 37.5% of the traditional circuit time (in gate delays).<<ETX>>","PeriodicalId":368020,"journal":{"name":"[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116403779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of a highly parallel AI processor using new multiple-valued MOS devices 基于新型多值MOS器件的高度并行AI处理器设计
[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic Pub Date : 1988-05-24 DOI: 10.1109/ISMVL.1988.5187
T. Hanyu, T. Higuchi
{"title":"Design of a highly parallel AI processor using new multiple-valued MOS devices","authors":"T. Hanyu, T. Higuchi","doi":"10.1109/ISMVL.1988.5187","DOIUrl":"https://doi.org/10.1109/ISMVL.1988.5187","url":null,"abstract":"A design for a highly parallel processor for real-time reasoning in artificial intelligence (AI) is presented. Knowledge is represented by an associative network based on multiple-valued logic, so that a universal representation can be achieved by varying the parameters between nodes. High-speed reasoning can be attributed to the parallel graph-search technique on this associative network. For its direct implementation, special MOS devices with threshold voltages that are controllable by the external input signals are used. For the four-valued associative network, it is demonstrated that the number of memory cells, cell interconnections, and transistors can be greatly reduced in comparison with the corresponding binary implementation.<<ETX>>","PeriodicalId":368020,"journal":{"name":"[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122634512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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