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[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic最新文献

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Ternary CMOS sequential circuits 三进制CMOS顺序电路
[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic Pub Date : 1988-05-24 DOI: 10.1109/ISMVL.1988.5188
X. Wu, F. Prosser
{"title":"Ternary CMOS sequential circuits","authors":"X. Wu, F. Prosser","doi":"10.1109/ISMVL.1988.5188","DOIUrl":"https://doi.org/10.1109/ISMVL.1988.5188","url":null,"abstract":"Threshold comparison, transmission, and union operations are discussed and used as the basis of a logic design procedure for CMOS ternary circuits. Some basic CMOS ternary circuits are used to design CMOS ternary flip-flops (tri-flops) such as the ternary latch and various master-slave tri-flops. These tri-flops have two additional binary inverse outputs with a fixed threshold. A modulo-9 up counter is presented as an example of sequential circuit design using these tri-flops.<<ETX>>","PeriodicalId":368020,"journal":{"name":"[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115002298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A discussion on the theory of logic value redundance 关于逻辑值冗余理论的讨论
[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic Pub Date : 1988-05-24 DOI: 10.1109/ISMVL.1988.5162
M. Hu, K. Smith
{"title":"A discussion on the theory of logic value redundance","authors":"M. Hu, K. Smith","doi":"10.1109/ISMVL.1988.5162","DOIUrl":"https://doi.org/10.1109/ISMVL.1988.5162","url":null,"abstract":"Logic value redundancy, a technique that differs from conventional redundancy techniques, is under development. It belongs to the same class of redundancy techniques as error-detecting and error-correcting codes. The concepts, theory, and applications of logic value redundancy are presented.<<ETX>>","PeriodicalId":368020,"journal":{"name":"[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126736571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Structural computer-aided design of current-mode CMOS logic circuits 电流型CMOS逻辑电路的结构计算机辅助设计
[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic Pub Date : 1988-05-24 DOI: 10.21236/ada608071
S. Onneweer, H. Kerkhoff, J. Butler
{"title":"Structural computer-aided design of current-mode CMOS logic circuits","authors":"S. Onneweer, H. Kerkhoff, J. Butler","doi":"10.21236/ada608071","DOIUrl":"https://doi.org/10.21236/ada608071","url":null,"abstract":"A set of CAD (computer-aided design) tools for the synthesis and layout generation of multiple-valued current-mode CMOS logic (CMCL) circuits is described. The synthesis method is based on the cost-table method. The general circuit structure, the cost-table functions, and the decomposition procedure used in the synthesis program are explained. The program is based on a logically complete set of basic elements for CMCL circuits. After circuit synthesis, the actual layout is generated using standard-cell IC design tools.<<ETX>>","PeriodicalId":368020,"journal":{"name":"[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122816922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Specific arithmetics in radices +/-4 以+/-4为基数的具体算术
[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic Pub Date : 1988-05-24 DOI: 10.1109/ISMVL.1988.5165
T. T. Dao
{"title":"Specific arithmetics in radices +/-4","authors":"T. T. Dao","doi":"10.1109/ISMVL.1988.5165","DOIUrl":"https://doi.org/10.1109/ISMVL.1988.5165","url":null,"abstract":"To accelerate binary arithmetics, algorithms in higher radices than two have been implemented. In particular, radices +or-4 present in many instances the optimum choice in terms of speed vs. complexity. In this context the author reviews Booth's algorithm for multiplication, nonrestoring redundant signed digit approaches to division and square root, and Knuth's scheme for complex arithmetic. He presents a novel way to do arithmetic on a quadtree representation of a 2-D image.<<ETX>>","PeriodicalId":368020,"journal":{"name":"[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116165608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The logical and probabilistic bases of the calculus of evidence 证据计算的逻辑和概率基础
[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic Pub Date : 1988-05-24 DOI: 10.1109/ISMVL.1988.5174
E. Ruspini
{"title":"The logical and probabilistic bases of the calculus of evidence","authors":"E. Ruspini","doi":"10.1109/ISMVL.1988.5174","DOIUrl":"https://doi.org/10.1109/ISMVL.1988.5174","url":null,"abstract":"Summary form only given. The approach proposed by R. Carnap (1962) to the development of logical bases for probability theory is applied to structures based on epistemic logic. The resulting structure, called the epistemic universe, consists of joint descriptions of possible states of the world as well as of the states of knowledge rational agents have regarding it. Special algebras of subsets of the epistemic universe are then defined. Probabilities defined over one of these classes, called the epistemic algebra (representing similar states of knowledge), are directly related to the basic functional structures of the Dempster-Shafer calculus of evidence: belief and mass assignment functions. Extensions of these probability functions to the truth algebra (representing true states of real world), must satisfy the well-known bounds of the Dempster-Shafer theory. Furthermore, these bounds are the best possible. Consideration of multiple agents leads both to more complex epistemic structures and to the derivation of a basic formula for the combination of knowledge, called the additive combination formula. From this formula and certain independence assumptions, Dempster's rule of combination is readily derived.<<ETX>>","PeriodicalId":368020,"journal":{"name":"[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116298515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Application of temporal logic to the assistance of hardware logic design 时间逻辑在辅助硬件逻辑设计中的应用
[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic Pub Date : 1988-05-24 DOI: 10.1109/ISMVL.1988.5182
M. Fujita
{"title":"Application of temporal logic to the assistance of hardware logic design","authors":"M. Fujita","doi":"10.1109/ISMVL.1988.5182","DOIUrl":"https://doi.org/10.1109/ISMVL.1988.5182","url":null,"abstract":"The specification of digital systems in temporal logic, a verification method between specification and gate-level designs, and a method for synthesizing state diagrams from specification are presented. Timing relations shown usually be timing diagrams can be described, and verification and synthesis can be done automatically. A hardware description language called Tokio, which is based on temporal logic and is an extension of Prolog, is also presented. The above techniques can be applied to Tokio.<<ETX>>","PeriodicalId":368020,"journal":{"name":"[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132466082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Probabilistic and fuzzy relational semantic systems in propositional approximate reasoning 命题近似推理中的概率和模糊关系语义系统
[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic Pub Date : 1988-05-24 DOI: 10.1109/ISMVL.1988.5175
J.A. Martin
{"title":"Probabilistic and fuzzy relational semantic systems in propositional approximate reasoning","authors":"J.A. Martin","doi":"10.1109/ISMVL.1988.5175","DOIUrl":"https://doi.org/10.1109/ISMVL.1988.5175","url":null,"abstract":"The notion of an RSS (relational semantic system) as a set of atomic propositions evaluated in the unit interval and functions representing complementation (negation n) and logical intersection (junctor j) is introduced. This concept is used to determine under what circumstances the models of fuzzy approximate reasoning can be embedded in a probability space. This situation includes most of the classical fuzzy-set-theoretical approaches. A straightforward way of representing the concept of conditioning for most fuzzy measures is obtained.<<ETX>>","PeriodicalId":368020,"journal":{"name":"[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130239963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
MCD-to-m-valued and m-valued-to-MCD converters mcd到m值和m值到mcd转换器
[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic Pub Date : 1988-05-24 DOI: 10.1109/ISMVL.1988.5196
H. Lu, S.C. Lee
{"title":"MCD-to-m-valued and m-valued-to-MCD converters","authors":"H. Lu, S.C. Lee","doi":"10.1109/ISMVL.1988.5196","DOIUrl":"https://doi.org/10.1109/ISMVL.1988.5196","url":null,"abstract":"Two general algorithms to perform conversions between m-valued (MV) numbers and m-nary-coded-decimal (MCD) numbers for any radix m>1 are proposed. Although the algorithms are described in terms of shift and addition operations, they can be implemented by serial-parallel bit-processing using read-only memories (ROMs). Formulas for computing the conversion speed are given. A comparison of the conversion speed for various different values of m is included.<<ETX>>","PeriodicalId":368020,"journal":{"name":"[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134163191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Almost orthogonal functions 几乎正交函数
[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic Pub Date : 1988-05-24 DOI: 10.1109/ISMVL.1988.5202
G. Epstein, R. Rao Loka
{"title":"Almost orthogonal functions","authors":"G. Epstein, R. Rao Loka","doi":"10.1109/ISMVL.1988.5202","DOIUrl":"https://doi.org/10.1109/ISMVL.1988.5202","url":null,"abstract":"Almost-orthogonal functions, which are obtained by perturbing orthogonal functions, do not exactly satisfy the orthogonality conditions. The notion of almost-orthogonal functions is explained with examples. An error analysis of expansion coefficients based on almost-orthogonal functions is given. Using examples derived from sinusoids, it is shown how computational advantage can be obtained by using almost-orthogonal functions in signal processing.<<ETX>>","PeriodicalId":368020,"journal":{"name":"[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130867598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS ternary ROM chip 一种CMOS三元ROM芯片
[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic Pub Date : 1988-05-24 DOI: 10.1109/ISMVL.1988.5195
Y. Cho, H. Mouftah
{"title":"A CMOS ternary ROM chip","authors":"Y. Cho, H. Mouftah","doi":"10.1109/ISMVL.1988.5195","DOIUrl":"https://doi.org/10.1109/ISMVL.1988.5195","url":null,"abstract":"A read-only memory (ROM) based on three-valued memory cells is presented. The ROM has been designed for use in a ternary digital system. It is a 2187*5 trit, contact-programmed device. A CMOS 3- mu m double-metal process has been used to implement the device.<<ETX>>","PeriodicalId":368020,"journal":{"name":"[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131202796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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