进位二进制加法的四元逻辑

[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic Pub Date : 1988-05-24 DOI:10.1109/ISMVL.1988.5186

M. A. Manzoul, A. Bommireddy

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引用次数: 2

摘要

讨论了四值逻辑在加速二进制加法运算中的作用。提出了一种完全由二进制门实现的改进型超前加法器电路。提出的n位加法器的速度在门延迟和扇入方面与传统的超前n位加法器进行了比较。结果表明，所提出的加法器在n决定的一定范围内速度更快。对于8位加法器，电路可以节省传统电路37.5%的时间(门延迟)。

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Quaternary logic for carry-lookahead binary addition

The role of the quaternary (four-valued) logic in speeding up the binary addition is discussed. An improved carry-lookahead adder circuit, which is completely realizable by binary gates, is presented. The speed of the proposed n-bit adder is compared to the traditional carry-lookahead n-bit adder in terms of gate delays and fan-in. Results show that the proposed adder is faster in certain ranges determined by n. For an 8-bit adder, the circuit can save 37.5% of the traditional circuit time (in gate delays).<>

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[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic

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