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Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)最新文献

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Gate-level simulation of digital circuits using multi-valued Boolean algebras 基于多值布尔代数的数字电路门级仿真
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480149
Scott Woods, G. Casinovi
{"title":"Gate-level simulation of digital circuits using multi-valued Boolean algebras","authors":"Scott Woods, G. Casinovi","doi":"10.1109/ICCAD.1995.480149","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480149","url":null,"abstract":"This paper describes an algorithm for the simulation of gate-level logic. Multiple logic levels are used to describe the state of each node. Each state corresponds to a different voltage level, and the number of levels to be used for a simulation is user-defined. This feature simplifies considerably the interface between a digital and an analog simulator. A DC solver is incorporated to find the initial operating point of a circuit before a transient analysis begins. This solver has the capability of finding the operating point of gates located in feedback loops. For transient analysis, a gate delay model that takes into account the slope of the input waveforms is used. The performance of the algorithm is demonstrated by simulations of a number of benchmark circuits.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122958402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A multiple-dominance switch-level model for simulation of short faults 用于模拟短故障的多主导开关级模型
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480202
P. Dahlgren
{"title":"A multiple-dominance switch-level model for simulation of short faults","authors":"P. Dahlgren","doi":"10.1109/ICCAD.1995.480202","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480202","url":null,"abstract":"Short faults in CMOS networks frequently give rise to intermediate node voltages. An efficient local algorithm is presented for event-driven switch-level simulation of CMOS networks in which intermediate signal values are common. The proposed model allows multiple dominant signals associated with the state of a node. The strength of several logical low and high signal contributions can thereby be taken into account when the logic state of a node is computed, which means that intermediate voltages can be handled more accurately. To demonstrate the usefulness of the multiple-dominance model in fault simulations, a new fault simulation algorithm is presented. Various common transistor-level fault types were simulated, and the results show that the number of discrepancies from electrical-level simulations is significantly reduced at a low computational cost.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132528837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Multi-level logic optimization of FSM networks FSM网络的多级逻辑优化
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480254
Huey-Yih Wang, R. Brayton
{"title":"Multi-level logic optimization of FSM networks","authors":"Huey-Yih Wang, R. Brayton","doi":"10.1109/ICCAD.1995.480254","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480254","url":null,"abstract":"Current approaches to compute and exploit the flexibility of a component in an FSM network are all at the symbolic level. Conventionally, exploitation of this flexibility relies on state minimizers for incompletely specified FSMs (ISFSMs) or pseudo non-deterministic FSMs (PNDFSM's). However, state-of-the art state minimizers cannot handle large ISFSMs or PNDFSMs. In addition, these exploitation techniques are at the symbolic level, not directly at the net-list logic level. We present a general approach to exploit exact or approximate flexibility directly at the net-list logic level, and we demonstrate that many sequential logic optimization techniques can be applied in exploitation. Moreover, we propose a new procedure for input don't care sequences. As a result, both computation and exploitation of input don't care sequences in larger FSM networks can be made efficient and effective. Finally, we give preliminary results on some artificially constructed FSM networks. Preliminary results indicate that our approach can be effective in reducing the size of a component of an FSM network.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131803180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Coping with RC(L) interconnect design headaches 处理RC(L)互连设计难题
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480019
L. Pileggi
{"title":"Coping with RC(L) interconnect design headaches","authors":"L. Pileggi","doi":"10.1109/ICCAD.1995.480019","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480019","url":null,"abstract":"Physical interconnect effects have a dominant impact on today's deep submicron IC designs. In this tutorial paper we will describe the technology trends which have brought about this interconnect dominance, then consider some of the modeling and analysis approximations available for both pre- and post-layout interconnect design. This coverage will not be an exhaustive summary, but one that is primarily focused on moment-based analysis techniques, from the Elmore delay, to the more recent advances in moment-matching approximations, and the corresponding nonlinear driver/load interfaces. Future modeling, analysis, and design challenges will be considered throughout this paper.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"653 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132053647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 65
Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits CMOS VLSI电路内部节点最大跃迁数的估计
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480142
Chin-Chi Teng, A. Hill, S. Kang
{"title":"Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits","authors":"Chin-Chi Teng, A. Hill, S. Kang","doi":"10.1109/ICCAD.1995.480142","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480142","url":null,"abstract":"In combinational logic circuits, a single switching event on the primary inputs may give rise to multiple switchings at the internal nodes. This glitching effect is caused primarily by unequal delay paths and results in increased power consumption and decreased device reliability. In this paper, we present a new algorithm to estimate the maximum number of transitions at internal nodes in combinational CMOS VLSI circuits. Unlike exhaustive simulation, our algorithm is based on the technique of propagating uncertainty waveforms throughout the circuit and using these waveforms to count the maximum switching activity at every node. Our approach guarantees a tight upper bound on the number of transitions which is necessary to assess the minimum circuit reliability lifetime and maximum power dissipation.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130743437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
A new algorithm for the design of stable higher order single loop sigma delta analog-to-digital converters 一种设计稳定的高阶单回路σ δ模数转换器的新算法
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480171
S. R. Kadivar, D. Schmitt-Landsiedel, H. Klar
{"title":"A new algorithm for the design of stable higher order single loop sigma delta analog-to-digital converters","authors":"S. R. Kadivar, D. Schmitt-Landsiedel, H. Klar","doi":"10.1109/ICCAD.1995.480171","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480171","url":null,"abstract":"This paper presents a new algorithm to attain optimized network scaling in single loop, 1 bit Sigma Delta Analog 1d Digital Converters (SD ADC) of order three or more. The algorithm is based on a novel mathematical description of stability and performance criteria of the SD ADC and on the application of nonlinear interactive optimization techniques. The feasibility of the new algorithm has been confirmed in practical implementations. The method brings new insight on the correlation between system stability, performance, system order and the choice of the network scaling. Our method is extendible to cascaded SD as well as SD based on filter topologies.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124233264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Impulse response fault model and fault extraction for functional level analog circuit diagnosis 用于功能级模拟电路诊断的脉冲响应故障模型及故障提取
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480195
C. Su, Yue-Tsang Chen, Shenshung Chiang
{"title":"Impulse response fault model and fault extraction for functional level analog circuit diagnosis","authors":"C. Su, Yue-Tsang Chen, Shenshung Chiang","doi":"10.1109/ICCAD.1995.480195","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480195","url":null,"abstract":"In this paper, a functional fault model for analog circuit diagnosis is proposed. A faulty module is modeled as a fault-free module in serial or in parallel with a fault module. To extract such a fault module, we adopt an iterative deconvolution technique to deconvolute the impulse response of the fault module from the faulty response. The test results show that with such a fault model and fault extraction technique the diagnostic resolution is improved significantly due to the separation of the fault and the system function. Moreover, such a fault model allows single-module fault tables to be applied to the diagnosis of a multi-module system.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"2005 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122918746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Test register insertion with minimum hardware cost 用最小的硬件成本测试寄存器插入
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.479998
A. P. Stroele, H. Wunderlich
{"title":"Test register insertion with minimum hardware cost","authors":"A. P. Stroele, H. Wunderlich","doi":"10.1109/ICCAD.1995.479998","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.479998","url":null,"abstract":"Implementing a built-in self-test by a test per clock scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a scheme is implemented by test registers, for instance BILBOs and CBILBOs, which are inserted into the circuit structure at appropriate places. An algorithm is presented which is able to find the cost optimal placement of test registers for nearly all the ISCAS'89 sequential benchmark circuits, and a suboptimal solution with slightly higher costs is obtained for all the circuits within a few minutes of computing time. The algorithm can also be applied to the Minimum Feedback Vertex Set problem in partial scan design, and an optimal solution is found for all the benchmark circuits. The resulting self-testable circuits are analyzed. It is found that often CBILBOs lead to a minimum hardware overhead and also simplify test scheduling and test control.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"469 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123282295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A high-level design and optimization tool for analog RF receiver front-ends 模拟射频接收器前端的高级设计和优化工具
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480170
J. Crols, S. Donnay, M. Steyaert, G. Gielen
{"title":"A high-level design and optimization tool for analog RF receiver front-ends","authors":"J. Crols, S. Donnay, M. Steyaert, G. Gielen","doi":"10.1109/ICCAD.1995.480170","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480170","url":null,"abstract":"This paper presents a high-level analysis and optimization tool for the design of analog RF receiver front-ends, which takes all design parameters and all aspects of performance degradation (noise, distortion, self-mixing...) into account. The simulations are performed in the spectral domain with a behavioral model library for the RF building blocks. The tool allows to explore alternative RF receiver topologies as well as to investigate design trade-offs within each topology. By having integrated the performance analysis routine within a simulated annealing optimization loop, the tool can also perform an optimal high-level synthesis of a given topology towards a specific application. It then determines the optimal specifications for the RF building blocks such that the required receiver signal quality is met while the overall power and/or area consumption is minimized.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124500865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 49
Efficient reduced-order modeling for the transient simulation of three-dimensional interconnect 三维互连体瞬态仿真的高效降阶建模
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.479988
M. Chou, Jacob K. White
{"title":"Efficient reduced-order modeling for the transient simulation of three-dimensional interconnect","authors":"M. Chou, Jacob K. White","doi":"10.1109/ICCAD.1995.479988","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.479988","url":null,"abstract":"Multipole-accelerated surface-volume methods have proved to be very efficient techniques for delay and cross-talk simulation of three-dimensional integrated circuit interconnect. However, to be efficiently combined with transistor circuitry in a SPICE-level simulation, reduced-order models which have accurate low-frequency behavior must be constructed. Asymptotic Waveform Evaluation (AWE) or Pade-via-Lanczos (PVL) algorithms can not be used directly to construct the reduced-order models from the surface-volume formulation, because the formulation generates dense matrices which are too expensive to factor. In this paper we describe a two-level approach to efficiently generating reduced-order models with accurate low frequency behavior. First, reduced-order models which match Taylor series terms at s=/spl infin/ are efficiently generated from the surface-volume formulation using an Arnoldi method, and then these fairly high-order models are used to efficiently construct lower-order models which snatch Taylor series terms at s=0. Examples are given to demonstrate the accuracy of the resultant low-order model.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125693247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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