发布求助
文献互助 智能选刊 最新文献

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)最新文献

筛选
英文 中文
Fault emulation: a new approach to fault grading 故障仿真:一种故障分级的新方法
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480203
K. Cheng, Shi-Yu Huang, W. Dai
{"title":"Fault emulation: a new approach to fault grading","authors":"K. Cheng, Shi-Yu Huang, W. Dai","doi":"10.1109/ICCAD.1995.480203","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480203","url":null,"abstract":"In this paper, we propose a method of using an FPGA-based emulation system for fault grading. The real-time simulation capability of a hardware emulator could significantly improve the run-time of fault grading, which is one of the most resource-intensive tasks in the design process. A serial fault emulation algorithm is employed and enhanced by two speed-up techniques. First, a set of independent faults can be emulated in parallel. Second, simultaneous injection of multiple dependent faults is also possible by adding extra supporting circuitry. Because the reconfiguration time spent on mapping the numerous faulty circuits into the FPGA boards could be the bottleneck of the whole process, using extra logic for injecting a large number of faults per configuration can reduce the number of reconfigurations, and thus, significantly improve the efficiency. Some modeling issues that are unique in the fault emulation environment are also addressed. The performance estimation indicates that this approach could be several orders of magnitude faster than the existing software approaches for large designs.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131306425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
A delay model for logic synthesis of continuously-sized networks 连续网络逻辑综合的延迟模型
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480156
J. Grodstein, E. Lehman, H. Harkness, B. Grundmann, Yosinori Watanabe
{"title":"A delay model for logic synthesis of continuously-sized networks","authors":"J. Grodstein, E. Lehman, H. Harkness, B. Grundmann, Yosinori Watanabe","doi":"10.1109/ICCAD.1995.480156","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480156","url":null,"abstract":"We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as constant and makes the cell's delay a linear function of load. Out model is based on a different, but equally fundamental linearity in the equation relating area, delay, and load: namely, we may keep a cell's delay constantly making its area a linear function of load. This allows us to technology map using a library with continuous device sizing, satisfies certain electrical noise and power constraints, and in certain cases is computationally simpler than a traditional model. We give results to support these claims. A companion paper uses the computational simplicity to explore a wide search space of algebraic factorings in a mapped network.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131313659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
Diagnosis of realistic bridging faults with single stuck-at information 基于单卡点信息的现实桥接故障诊断
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480011
D. B. Lavo, Brian Chess, T. Larrabee, F. Ferguson
{"title":"Diagnosis of realistic bridging faults with single stuck-at information","authors":"D. B. Lavo, Brian Chess, T. Larrabee, F. Ferguson","doi":"10.1109/ICCAD.1995.480011","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480011","url":null,"abstract":"Precise failure analysis requires accurate fault diagnosis. A previously proposed method for diagnosing bridging faults using single stuck-at dictionaries was applied only to small circuits, produced large and imprecise diagnoses, and did not take into account the Byzantine Generals Problem for bridging faults. We analyze the original technique and improve it by introducing the concepts of match restriction, match requirement, and failure recovery. Our new technique, which requires no information other than that used by standard stuck-at methods, produces diagnoses that are an order of magnitude smaller than those produced by the original technique and produces many fewer misleading diagnoses than that of traditional stuck-at diagnosis.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124659038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 116
Circuit partitioning with logic perturbation 具有逻辑摄动的电路划分
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480198
D. I. Cheng, Chih-Chang Lin, M. Marek-Sadowska
{"title":"Circuit partitioning with logic perturbation","authors":"D. I. Cheng, Chih-Chang Lin, M. Marek-Sadowska","doi":"10.1109/ICCAD.1995.480198","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480198","url":null,"abstract":"Traditionally, the circuit partitioning problem is done by first modeling a circuit as a graph and then partitioning is performed on the modeling graph. Using the concept of alternative wires, we propose an efficient method that is able to preserve a local optimal solution in the graph domain while a different graph, representing the same circuit, is generated. When a conventional graph partitioning technique reaches a local optimal solution, our proposed technique generates a different graph that is logically equivalent to the original circuit, and that has equal or better partitioning solution. Faced with a different graph which is newly generated together with a currently good partitioning solution, a conventional graph partitioning technique may then escape from the optimum and continue searching for better solutions in a different graph domain. The proposed technique can be combined with almost any graph partitioner. Experiments show encouraging results.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132071369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Dynamic test signal design for analog ICs 模拟ic的动态测试信号设计
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480194
G. Devarayanadurg, M. Soma
{"title":"Dynamic test signal design for analog ICs","authors":"G. Devarayanadurg, M. Soma","doi":"10.1109/ICCAD.1995.480194","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480194","url":null,"abstract":"In this paper we present an approach to construct dynamic test signals for analog circuits. Using the integral measure for characterizing time-domain signals, we extend the minmax formulation of the static test problem to the dynamic case. A sub-optimal solution strategy, similar to dynamic programming methods is used to construct the test waveforms. The approach presented here may be used to construct input signals for an on-chip test scheme or for the selection of an external stimulus applied through an arbitrary waveform generator.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134647438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
Performance-driven simultaneous place and route for island-style FPGAs 性能驱动的岛式fpga同步放置和路由
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480137
Sudip Nag, Rob A. Rutenbar
{"title":"Performance-driven simultaneous place and route for island-style FPGAs","authors":"Sudip Nag, Rob A. Rutenbar","doi":"10.1109/ICCAD.1995.480137","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480137","url":null,"abstract":"Sequential place and route tools for FPGAs are inherently weak at addressing both wirability and timing optimizations. This is primarily due to the difficulty of accurately predicting wirability and delay during placement. A new performance-driven simultaneous placement/routing technique has been developed for island-style FPGA designs. On a set of industrial designs for Xilinx 4000-series FPGAs, our scheme produces 100% routed designs with 8%-15% improvement in delay when compared to the Xilinx XACT5.0 place and route system.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"103 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133173968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Architectural partitioning of control memory for application specific programmable processors 用于特定应用程序的可编程处理器的控制存储器的体系结构分区
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480166
Wei Zhao, C. Papachristou
{"title":"Architectural partitioning of control memory for application specific programmable processors","authors":"Wei Zhao, C. Papachristou","doi":"10.1109/ICCAD.1995.480166","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480166","url":null,"abstract":"Because of programmability of Application Specific Programmable Processors (ASPPs), microcode-based control is effectively used to drive ASPP datapaths for different applications. In ASPPs, each application needs a separate microprogram resulting in large microcode memory. This paper proposes a distributed microcode memory model in which only distinct microcodes are stored in each separate memory module to save memory area. A hierarchical clustering approach is also proposed for the design of this distributed microcode memory. Experimental results indicate this approach is especially well suited for ASPP microcode memory design because of the existence of repetitive microcodes across multiple behaviors.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127290618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An empirical model for accurate estimation of routing delay in FPGAs fpga中精确估计路由延迟的经验模型
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480136
T. Karnik, S. Kang
{"title":"An empirical model for accurate estimation of routing delay in FPGAs","authors":"T. Karnik, S. Kang","doi":"10.1109/ICCAD.1995.480136","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480136","url":null,"abstract":"We present an empirical routing delay model for estimating interconnection delays in FPGAs. We assume that the routing delay is a function of interPLC distances, circuit size, fanout of the net and routing congestion in the channel. We performed extensive simulations of various circuits to generate a sufficiently large dataset. Our method estimates delays by reading the average value tables and interpolating the values, if necessary. We present a rigorous statistical justification of this delay model. Our results show that our method predicts the delays within 20% of actual and it far outperforms all other existing techniques.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128052510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Pattern generation for a deterministic BIST scheme 确定性BIST模式的模式生成
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.479997
S. Hellebrand, Birgit Reeb, S. Tarnick, H. Wunderlich
{"title":"Pattern generation for a deterministic BIST scheme","authors":"S. Hellebrand, Birgit Reeb, S. Tarnick, H. Wunderlich","doi":"10.1109/ICCAD.1995.479997","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.479997","url":null,"abstract":"Recently a deterministic built-in self-test scheme has been presented based on reseeding of multiple-polynomial linear feedback shift registers. This scheme encodes deterministic test sets at distinctly lower costs than previously known approaches. In this paper it is shown how this scheme can be supported during test pattern generation. The presented ATPG algorithm generates test sets which can be encoded very efficiently. Experiments show that the area required for synthesizing a BIST scheme that encodes these patterns is significantly less than the area needed for storing a compact test set. Furthermore, it is demonstrated that the proposed approach of combining ATPG and BIST synthesis leads to a considerably reduced hardware overhead compared to encoding a conventionally generated test set.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124310249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 155
Background memory management for dynamic data structure intensive processing systems 动态数据结构密集处理系统的后台内存管理
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) Pub Date : 1995-12-01 DOI: 10.1109/ICCAD.1995.480165
G. D. Jong, Bill Lin, C. Verdonck, S. Wuytack, F. Catthoor
{"title":"Background memory management for dynamic data structure intensive processing systems","authors":"G. D. Jong, Bill Lin, C. Verdonck, S. Wuytack, F. Catthoor","doi":"10.1109/ICCAD.1995.480165","DOIUrl":"https://doi.org/10.1109/ICCAD.1995.480165","url":null,"abstract":"Telecommunication network management applications often require application-specific ICs that use large dynamically allocated stored data structures. Currently available hardware synthesis environments typically do not support dynamic data structure concepts and their associated memory synthesis problems. In this paper we address the background memory management task in a hardware design trajectory, which includes allocation of a distributed memory architecture, assignment and mapping of abstract data structures to memories, and synthesis of dynamic management behavior. With this approach to explore for the optimal memory architecture, the design entry point is lifted to a higher level than currently used for behavioral synthesis, as the specification can be a high-level program using data abstraction. The power of our approach will be substantiated on an industrial high-performance telecommunication ASIC design.","PeriodicalId":367501,"journal":{"name":"Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121522115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信