A new algorithm for the design of stable higher order single loop sigma delta analog-to-digital converters

Abstract

This paper presents a new algorithm to attain optimized network scaling in single loop, 1 bit Sigma Delta Analog 1d Digital Converters (SD ADC) of order three or more. The algorithm is based on a novel mathematical description of stability and performance criteria of the SD ADC and on the application of nonlinear interactive optimization techniques. The feasibility of the new algorithm has been confirmed in practical implementations. The method brings new insight on the correlation between system stability, performance, system order and the choice of the network scaling. Our method is extendible to cascaded SD as well as SD based on filter topologies.