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2014 IEEE COOL Chips XVII最新文献

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A low power NoC router using the marching memory through type 一种低功耗NoC路由器，使用行军存储器直通类型
2014 IEEE COOL Chips XVII Pub Date : 2014-04-14 DOI: 10.1109/CoolChips.2014.6842960
Ryota Yasudo, Takahiro Kagami, H. Amano, Y. Nakase, Masashi Watanabe, T. Oishi, Toru Shimizu, Tadao Nakamura
{"title":"A low power NoC router using the marching memory through type","authors":"Ryota Yasudo, Takahiro Kagami, H. Amano, Y. Nakase, Masashi Watanabe, T. Oishi, Toru Shimizu, Tadao Nakamura","doi":"10.1109/CoolChips.2014.6842960","DOIUrl":"https://doi.org/10.1109/CoolChips.2014.6842960","url":null,"abstract":"We have concluded that with a router using MMTH the power consumption is associated with the bit change rate of the data, and when NAS parallel benchmarks work on NoC, it is reduced by 42.4% on average at 2GHz compared with a traditional FIFO implementation. The performance degradation caused by the delay of the reading time can be mostly saved by the look-ahead technique in the router.","PeriodicalId":366328,"journal":{"name":"2014 IEEE COOL Chips XVII","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128909745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Embedded SRAM and Cortex-M0 core with backup circuits using a 60-nm crystalline oxide semiconductor for power gating 嵌入式SRAM和Cortex-M0核心与备用电路使用60纳米晶体氧化物半导体电源门控
2014 IEEE COOL Chips XVII Pub Date : 2014-04-14 DOI: 10.1109/CoolChips.2014.6842955
H. Tamura, K. Kato, T. Ishizu, T. Onuki, W. Uesugi, Takuro Ohmaru, K. Ohshima, Hidetomo Kobayashi, S. Yoneda, A. Isobe, N. Tsutsui, S. Hondo, Yasutaka Suzuki, Y. Okazaki, T. Atsumi, Y. Shionoiri, Y. Maehashi, G. Goto, M. Fujita, James Myers, P. Korpinen, J. Koyama, Yoshitaka Yamamoto, S. Yamazaki
{"title":"Embedded SRAM and Cortex-M0 core with backup circuits using a 60-nm crystalline oxide semiconductor for power gating","authors":"H. Tamura, K. Kato, T. Ishizu, T. Onuki, W. Uesugi, Takuro Ohmaru, K. Ohshima, Hidetomo Kobayashi, S. Yoneda, A. Isobe, N. Tsutsui, S. Hondo, Yasutaka Suzuki, Y. Okazaki, T. Atsumi, Y. Shionoiri, Y. Maehashi, G. Goto, M. Fujita, James Myers, P. Korpinen, J. Koyama, Yoshitaka Yamamoto, S. Yamazaki","doi":"10.1109/CoolChips.2014.6842955","DOIUrl":"https://doi.org/10.1109/CoolChips.2014.6842955","url":null,"abstract":"A chip of embedded SRAM having backup circuits using a 60-nm c-axis aligned crystalline oxide semiconductor (CAAC-OS) such as CAAC indium-gallium-zinc oxide (CAAC-IGZO) and Cortex-M0 core having flip-flops with CAAC-OS backup circuits is fabricated. The SRAM and M0 core can retain data using the backup circuits during power-off; thus, they can perform power gating (PG) with backup time of 100 ns and recovery time of 10 clock cycles (including data restoration time (100 ns)). Further, memory cell area and performance in combining a 45-nm Si SRAM memory cell with 60-nm CAAC-OS are estimated to have negligible overhead.","PeriodicalId":366328,"journal":{"name":"2014 IEEE COOL Chips XVII","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131660781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Panel discussions: Toward wearable computing era, how COOL chip architecture and tools will evolve? 小组讨论:面向可穿戴计算时代，COOL芯片架构和工具将如何发展?
2014 IEEE COOL Chips XVII Pub Date : 2014-04-14 DOI: 10.1109/CoolChips.2014.6842948
F. Arakawa
{"title":"Panel discussions: Toward wearable computing era, how COOL chip architecture and tools will evolve?","authors":"F. Arakawa","doi":"10.1109/CoolChips.2014.6842948","DOIUrl":"https://doi.org/10.1109/CoolChips.2014.6842948","url":null,"abstract":"Now we are enjoying the mobile computing era mainly with smart phones. This is a fruit of the continuous downsizing of computing devices, and further downsizing will realize a wearable computing era. Some wearable devices have been already available or announced today, and the shift to the new era is ongoing. We can enjoy a network infrastructure in many situations, although its speed, response time, or dependability is not always enough, and cloud computing is now popular approach to get extra computing power for client devices. So, we must consider how and from where we should get computing power to realize a good wearable computing device that will make new application enjoyable. An embedded processor of the device should have the features tuned for the device and different from that of a mobile device, and low power is one of the key features. Under such backgrounds, we will discuss how COOL chip architectures and tools will evolve toward wearable computing era.","PeriodicalId":366328,"journal":{"name":"2014 IEEE COOL Chips XVII","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116267917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Parallel design of control systems utilizing dead time for embedded multicore processors 利用死区时间的嵌入式多核处理器控制系统并行设计
2014 IEEE COOL Chips XVII Pub Date : 2014-04-14 DOI: 10.1109/CoolChips.2014.6842947
Yuta Suzuki, K. Sata, J. Kako, K. Yamaguchi, F. Arakawa, M. Edahiro
{"title":"Parallel design of control systems utilizing dead time for embedded multicore processors","authors":"Yuta Suzuki, K. Sata, J. Kako, K. Yamaguchi, F. Arakawa, M. Edahiro","doi":"10.1109/CoolChips.2014.6842947","DOIUrl":"https://doi.org/10.1109/CoolChips.2014.6842947","url":null,"abstract":"This paper presents a parallelization method utilizing dead time to implement higher precision control systems on multi-core processors. It is known that dead time is hard to handle with in control systems. In our method, the dead time is explicitly represented as delay blocks of models such as Simulink. Then, these delay blocks are distributed to the overall systems with equivalent transformation, so that the system can be simulated or executed in pipeline parallel. With a spring-mass-damper model, our technique accomplishes ×3.4 performance acceleration on an ideal four-core simulation, and ×1.8 on cycle-accurate simulator of a four-core embedded processor as a threaded application on a real time operating system.","PeriodicalId":366328,"journal":{"name":"2014 IEEE COOL Chips XVII","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121990442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A task-level pipelined many-SIMD augmented reality processor with congestion-aware network-on-chip scheduler 具有感知拥塞的片上网络调度程序的任务级流水线多simd增强现实处理器
2014 IEEE COOL Chips XVII Pub Date : 2014-04-14 DOI: 10.1109/CoolChips.2014.6842959
Gyeonghoon Kim, Seongwook Park, K. Lee, Youchang Kim, Injoon Hong, Kyeongryeol Bong, Dongjoo Shin, Sungpill Choi, Junyoung Park, H. Yoo
{"title":"A task-level pipelined many-SIMD augmented reality processor with congestion-aware network-on-chip scheduler","authors":"Gyeonghoon Kim, Seongwook Park, K. Lee, Youchang Kim, Injoon Hong, Kyeongryeol Bong, Dongjoo Shin, Sungpill Choi, Junyoung Park, H. Yoo","doi":"10.1109/CoolChips.2014.6842959","DOIUrl":"https://doi.org/10.1109/CoolChips.2014.6842959","url":null,"abstract":"A 36 Heterogeneous multicore processor is proposed to accelerate recognition-based markerless augmented reality. To enable a real-time operation of the proposed augmented reality, task-level pipelined multicore architecture with DLP/TLP optimized SIMD processing elements is implemented. In addition, the multicore employs a congestion-aware network-on-chip scheduler for 2D-mesh network-on-chip to support massive internal data transaction caused by task-level pipeline. As a result, it achieves 1.22TOPS peak performance and 1.57TOPS/W energy-efficiency, which are 88% and 76% improvement over a state-of-the-art augmented reality processor, for 30fps 720p test input video.","PeriodicalId":366328,"journal":{"name":"2014 IEEE COOL Chips XVII","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128176673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Special session speaker's biography 特别会议发言人简介
2014 IEEE COOL Chips XVII Pub Date : 1900-01-01 DOI: 10.1109/coolchips.2015.7158529
M. Ideno, I. Kostarnov, Dirk Seynhaeve
{"title":"Special session speaker's biography","authors":"M. Ideno, I. Kostarnov, Dirk Seynhaeve","doi":"10.1109/coolchips.2015.7158529","DOIUrl":"https://doi.org/10.1109/coolchips.2015.7158529","url":null,"abstract":"Mr. Masaaki Ideno is a Japan and Asia-pacific regional manager of Processor Designer product at Synopsys. He has experience at ARC international (configurable processor) and IPFlex (dynamically reconfigurable processor) before joining to CoWare in 2006. In 2010, CoWare is merged to Synopsys and he has continued Processor Designer business until now. He graduated Tokyo Kogakuin Colledge of Computer Technology in 1987.","PeriodicalId":366328,"journal":{"name":"2014 IEEE COOL Chips XVII","volume":"195 3-4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114027207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Message from the advisory committee chair 咨询委员会主席的话
2014 IEEE COOL Chips XVII Pub Date : 1900-01-01 DOI: 10.1109/CoolChips.2014.6842940
Tadao Nakamura
{"title":"Message from the advisory committee chair","authors":"Tadao Nakamura","doi":"10.1109/CoolChips.2014.6842940","DOIUrl":"https://doi.org/10.1109/CoolChips.2014.6842940","url":null,"abstract":"On behalf of the advisory committee of COOL Chips XVII, I extend greetings to each of the conference attendees. The productive goal of this conference is to be part of the premier/leading conference series on microprocessor architecture and technology. This rapidly growing field still regularly and aggressively produces innovative ideas and corresponding products for the cyber world around us day by day.","PeriodicalId":366328,"journal":{"name":"2014 IEEE COOL Chips XVII","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128188948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Message from the organizing committee chair 来自组委会主席的信息
2014 IEEE COOL Chips XVII Pub Date : 1900-01-01 DOI: 10.1109/CoolChips.2014.6842939
Hiroaki Kobayashi
{"title":"Message from the organizing committee chair","authors":"Hiroaki Kobayashi","doi":"10.1109/CoolChips.2014.6842939","DOIUrl":"https://doi.org/10.1109/CoolChips.2014.6842939","url":null,"abstract":"It is my pleasure to welcome you to the COOL Chips XVII, the 17th IEEE Symposium on Low-Power and High-Speed Chips. COOL Chips Conference Series started in 1998, which was held in Tokyo as a one-day event of invited talks only. Now COOL Chips is a three-day event fully sponsored by IEEE Computer Society, which covers not only the chip architecture design, but also software technologies at system software and application levels.","PeriodicalId":366328,"journal":{"name":"2014 IEEE COOL Chips XVII","volume":"26 25","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133425139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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