Yuta Suzuki, K. Sata, J. Kako, K. Yamaguchi, F. Arakawa, M. Edahiro
{"title":"Parallel design of control systems utilizing dead time for embedded multicore processors","authors":"Yuta Suzuki, K. Sata, J. Kako, K. Yamaguchi, F. Arakawa, M. Edahiro","doi":"10.1109/CoolChips.2014.6842947","DOIUrl":null,"url":null,"abstract":"This paper presents a parallelization method utilizing dead time to implement higher precision control systems on multi-core processors. It is known that dead time is hard to handle with in control systems. In our method, the dead time is explicitly represented as delay blocks of models such as Simulink. Then, these delay blocks are distributed to the overall systems with equivalent transformation, so that the system can be simulated or executed in pipeline parallel. With a spring-mass-damper model, our technique accomplishes ×3.4 performance acceleration on an ideal four-core simulation, and ×1.8 on cycle-accurate simulator of a four-core embedded processor as a threaded application on a real time operating system.","PeriodicalId":366328,"journal":{"name":"2014 IEEE COOL Chips XVII","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE COOL Chips XVII","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CoolChips.2014.6842947","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper presents a parallelization method utilizing dead time to implement higher precision control systems on multi-core processors. It is known that dead time is hard to handle with in control systems. In our method, the dead time is explicitly represented as delay blocks of models such as Simulink. Then, these delay blocks are distributed to the overall systems with equivalent transformation, so that the system can be simulated or executed in pipeline parallel. With a spring-mass-damper model, our technique accomplishes ×3.4 performance acceleration on an ideal four-core simulation, and ×1.8 on cycle-accurate simulator of a four-core embedded processor as a threaded application on a real time operating system.