2014 IEEE COOL Chips XVII最新文献

A low power DRAM refresh control scheme for 3D memory cube 一种用于三维存储立方体的低功耗DRAM刷新控制方案

2014 IEEE COOL Chips XVII Pub Date : 2014-04-14 DOI: 10.1109/CoolChips.2014.6842950

Ying Wang, Yinhe Han, Huawei Li

引用次数: 2

Aggressive use of Deep Sleep mode in low power embedded systems 在低功耗嵌入式系统中积极使用深度睡眠模式

2014 IEEE COOL Chips XVII Pub Date : 2014-04-14 DOI: 10.1109/CoolChips.2014.6842956

Jun'ichi Segawa, Yusuke Shirota, K. Fujisaki, Tetsuro Kimura, Tatsunori Kanai

引用次数: 4

An energy optimization method for vector processing mechanisms 矢量加工机构的能量优化方法

2014 IEEE COOL Chips XVII Pub Date : 2014-04-14 DOI: 10.1109/CoolChips.2014.6842957

Ye Gao, Masayuki Sato, Ryusuke Egawa, H. Takizawa, Hiroaki Kobayashi

引用次数: 0

A fine grained power management supported by just-in-time compiler 实时编译器支持的细粒度电源管理

2014 IEEE COOL Chips XVII Pub Date : 2014-04-14 DOI: 10.1109/CoolChips.2014.6842958

Motoki Wada, Mikiko Sato, M. Namiki

引用次数: 0

Establishing a standard interface between multi-manycore and software tools - SHIM 建立多核和软件工具之间的标准接口- SHIM

2014 IEEE COOL Chips XVII Pub Date : 2014-04-14 DOI: 10.1109/CoolChips.2014.6842946

Masaki Kondo, F. Arakawa, M. Edahiro

引用次数: 8

A flexibly fault-tolerant FU array processor and its self-tuning scheme to locate permanently defective unit 一种灵活容错FU阵列处理器及其定位永久故障单元的自调谐方案

2014 IEEE COOL Chips XVII Pub Date : 2014-04-14 DOI: 10.1109/CoolChips.2014.6842951

Jun Yao, Y. Nakashima, Mitsutoshi Saito, Yohei Hazama, Ryosuke Yamanaka

引用次数: 1

Language runtime support for NVM/DRAM hybrid main memory NVM/DRAM混合主存的语言运行时支持

2014 IEEE COOL Chips XVII Pub Date : 2014-04-14 DOI: 10.1109/CoolChips.2014.6842949

Gaku Nakagawa, S. Oikawa

引用次数: 5

Kernel data race detection using debug register in Linux Linux中使用调试寄存器的内核数据争用检测

2014 IEEE COOL Chips XVII Pub Date : 2014-04-14 DOI: 10.1109/CoolChips.2014.6842953

Yunyun Jiang, Yi Yang, Tian Xiao, Tianwei Sheng, Wenguang Chen

引用次数: 3

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology perpetual Mobile 32位CPU, 13.4pJ/cycle, 0.14µA休眠电流，采用反向体偏置辅助65nm SOTB CMOS技术

2014 IEEE COOL Chips XVII Pub Date : 2014-04-14 DOI: 10.1109/CoolChips.2014.6842954

K. Ishibashi, N. Sugii, K. Usami, H. Amano, Kazutoshi Kobayashi, C. Pham, H. Makiyama, Yoshiki Yamamoto, H. Shinohara, T. Iwamatsu, Y. Yamaguchi, H. Oda, T. Hasegawa, S. Okanishi, H. Yanagita, S. Kamohara, M. Kadoshima, K. Maekawa, T. Yamashita, Duc-Hung Le, T. Yomogita, M. Kudo, K. Kitamori, Shuya Kondo, Yuuki Manzawa

引用次数: 14

A globally asynchronous locally synchronous DMR architecture for aggressive low-power fault toleration 一种全局异步局部同步DMR体系结构，用于积极的低功耗容错

2014 IEEE COOL Chips XVII Pub Date : 2014-04-14 DOI: 10.1109/CoolChips.2014.6842952

Yuttakon Yuttakonkit, Jun Yao, Y. Nakashima

{"title":"A globally asynchronous locally synchronous DMR architecture for aggressive low-power fault toleration","authors":"Yuttakon Yuttakonkit, Jun Yao, Y. Nakashima","doi":"10.1109/CoolChips.2014.6842952","DOIUrl":"https://doi.org/10.1109/CoolChips.2014.6842952","url":null,"abstract":"Recently, dual or triple modular redundancy (DMR/TMR) has been commonly used in high-end server or special environment targeted microprocessors to mitigate single event effects (SEEs), as the miniaturized transistors tend to be more vulnerable to SEEs. However, facing the issue that DMR and TMR usually add remarkable pressures to the power consumption due to the highly redundant executions, this work specially provides an architectural solution to introduce aggressive dynamic voltage scaling (DVS) and Razor-FF on DMR architecture to moderate the total energy. As the traditional DMR architecture with a globally synchronous clock will have visible performance down-gradation when DVS and Razor-FF are used, in this work, we propose a DMR processor architecture that uses dedicated clocks on each DMR module, following a globally asynchronous locally synchronous (GALS) execution fashion. In the execution, due to the possible timing faults from the aggressively lowered voltage, the two modules may experience a dynamically phase-shift clock frequency. Our GALS DMR approach is assembled with FIFOs and delay buffers to conceal the effect from this phase-shift and thereby the performance impact is largely alleviated. Compared to the traditional synchronous DMR system, we can have around 10% performance improvement by this asynchronous scheme when a same power reduction ratio is assumed. Also, we have aggressively turned down the voltage and achieved a 12% better MIPS/W than the previous DMR without major performance influence.","PeriodicalId":366328,"journal":{"name":"2014 IEEE COOL Chips XVII","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123479339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0