A low power DRAM refresh control scheme for 3D memory cube

Abstract

We propose a low power refresh control scheme for 3D stacked DRAM memory, which leverages the data-pattern dependence characteristics of the cells' Retention-Time to squeeze the margin of refresh interval. It is a systematic approach that uses our proposed Retention-Time (RT) detection mechanism to capture the bottleneck that contributes to over-frequent refresh operations: “weak” cells with relatively shorter Retention-Time than others. With the help of memory scrubbers and Error Correction Pointer (ECP) table integrated on logic base of 3D memory cube, we can avoid the worst-case operation by locating the true “weak” cells sensitized by application and adapting the refresh rate to the data layout under our loop-based control algorithm. As shown in experiments, the method dramatically saves memory energy and bandwidth consumption.