Proceedings of the International Conference on Multichip Modules最新文献_第3页

Interconnected Mesh Power System, (IMPS) A Packaging and Interconnection Application 互联网状电力系统(IMPS)的封装与互联应用

Proceedings of the International Conference on Multichip Modules Pub Date : 1994-04-13 DOI: 10.1109/ICMCM.1994.753549

C. V. Reynolds, L. Schaper

引用次数: 1

An ATM Switching Module using MCM-C Technology 基于MCM-C技术的ATM交换模块

Proceedings of the International Conference on Multichip Modules Pub Date : 1994-04-13 DOI: 10.1109/ICMCM.1994.753539

M. Yamada, Y. Otsuki, T. Kikuchi, H. Shibuya

引用次数: 1

Accurate I/O Models for High Speed Digital Design Using Spice Controlled Sources 使用香料控制源的高速数字设计的精确I/O模型

Proceedings of the International Conference on Multichip Modules Pub Date : 1994-04-13 DOI: 10.1109/ICMCM.1994.753605

R. Goyal

引用次数: 0

Demonstration of a High Heat Removal Cvd Diamond Substrate Edge-Cooled Multichip Module 高散热Cvd金刚石基板边缘冷却多芯片模块的演示

Proceedings of the International Conference on Multichip Modules Pub Date : 1994-04-13 DOI: 10.1109/ICMCM.1994.753618

D. Peterson, J. Sweet, D.D. Andaleon, R. F. Renzi, D. Johnson

{"title":"Demonstration of a High Heat Removal Cvd Diamond Substrate Edge-Cooled Multichip Module","authors":"D. Peterson, J. Sweet, D.D. Andaleon, R. F. Renzi, D. Johnson","doi":"10.1109/ICMCM.1994.753618","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753618","url":null,"abstract":"A single substrate intended for a 3-dimensional (3D) edge-cooled multichip module (MCM) has been built and thermally tested. The substrate, with dimensions 1.9 in. by 2 in., is mounted in a fluid cooled block at one end. To test this cooling architecture and verify the accuracy of thermal models, we constructed thermal test modules using alumina (Al/sub 2/O/sub 3/), aluminum nitride (AIN), and CVD diamond substrate materials. Each module was populated with an array of 16 Sandia ATC03 test chips with resistive heaters and temperature sensing diode thermometers. Comparative measurements of the 3 substrates were made in which the top row of 4 die were heated at 5 W each for a total of 20 W. The maximum temperature differences between the heated die and the interface with the cold chuck, /spl Delta/T/sub JS/, were 24, 126, and 265/spl deg/C for diamond, AIN and Al/sub 2/O/sub 3/, respectively. Measurements on the diamond thermal test module, uniformly heated at a total power of 45 W, gave a measured substrate-to-sink temperature of /spl Delta/T /spl AP/ 20/spl deg/C. An extrapolation of our experimental data indicates that the diamond edge-cooled substrate could dissipate a total power /spl AP/ 192 W for a maximum junction-to-ambient temperature of /spl Delta/T/sub JA/ /spl AP/ 124/spl deg/C. If multiple substrates were 3 mounted in the fluid cooled block, spaced 0.075 in. apart, the volumetric power density would be about 850 W/in/sup 3/.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129613060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

A Cost-Effective Wafer-Level Burn-In Technology 具有成本效益的晶圆级老化技术

Proceedings of the International Conference on Multichip Modules Pub Date : 1994-04-13 DOI: 10.1109/ICMCM.1994.753526

D. Tuckerman, B. Jarvis, Chang-Ming Lin, P. Patel, M. Hunt

引用次数: 6

A Large Format Modified TEA CO/sub 2/ Laser Based Process for Cost Effective Small Via Generation 一种大幅面改进TEA CO/sub 2/激光工艺，具有成本效益的小通孔生成

Proceedings of the International Conference on Multichip Modules Pub Date : 1994-04-13 DOI: 10.1109/ICMCM.1994.753577

J. Morrison, T. Tessier, B. Gu

引用次数: 2

A Large Area, 3-D Stackable, Mcm-D on C Signal Processor C信号处理器上的大面积三维可堆叠Mcm-D

Proceedings of the International Conference on Multichip Modules Pub Date : 1994-04-13 DOI: 10.1109/ICMCM.1994.753615

L. Arndt

{"title":"A Large Area, 3-D Stackable, Mcm-D on C Signal Processor","authors":"L. Arndt","doi":"10.1109/ICMCM.1994.753615","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753615","url":null,"abstract":"Military applications for MCMs often require non-standard form factors tailored to fit the unique configurations of military systems. Size and weight requirements may further restrict the use of standard packaging and interconnect methods such as the typical SMT packages mounted on PWBs and backplanes. Cost and design cycle time considerations however argue in favor of standard configurations which can be used in multiple applications without incurring significant NRE costs or risks for each new application. An MCM approach will be presented which uses polymer thin film HDI deposited onto an LTCC substrate to provide a flexible form factor and a very high functional density, while maintaining the advantages of a standard, proven architecture and a fixed HDI layout. The HDI provides all internal chip-to-chip interconnect, while the LTCC acts as the package floor, redistributes primary I/O, and provides physical conformance to each target system. Hermetic sealing of the chips and HDI is accomplished by routinely brazing a Kovar seal ring onto the LTCC and subsequently seam welding a Kovar lid into place. This configuration also provides an I/O pad array interface which tends itself well to direct 3-D stacking of multiple MCMs in a \"building block\" fashion using only connectors but no PWB or backplane. MCMs have been successfully fabricated at two different HDI foundries, using Alumina substrates, while LTCC / HDI materials and processing techniques were matured. Testing of these MCMs has been successful with demonstrated performance superior to the PWB version of the circuit.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129912653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Ball Grid Array Ceramic Packages 球栅阵列陶瓷封装

Proceedings of the International Conference on Multichip Modules Pub Date : 1994-04-13 DOI: 10.1109/ICMCM.1994.753598

P. Danner

引用次数: 1

Development of a Burn-in and Test Process for Producing Known-Good-Die 一种生产已知质量模具的磨损和测试工艺的开发

Proceedings of the International Conference on Multichip Modules Pub Date : 1994-04-13 DOI: 10.1109/ICMCM.1994.753524

L. Prokopchak, J. Wrenn

引用次数: 1

A New Approach to Produce Cost-effective Known Good Die 一种生产具有成本效益的已知优良模具的新方法

Proceedings of the International Conference on Multichip Modules Pub Date : 1994-04-13 DOI: 10.1109/ICMCM.1994.753522

W. Kim, S. Lee, I. Hyun, K. Lee, J.M. Park

{"title":"A New Approach to Produce Cost-effective Known Good Die","authors":"W. Kim, S. Lee, I. Hyun, K. Lee, J.M. Park","doi":"10.1109/ICMCM.1994.753522","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753522","url":null,"abstract":"Known good die is an enabling technology for the application on the wide range of electronic industry especially for multichip module application. Wafer level burn-in is an ideal methodology to produce KGD's, but there needs a considerable amount of time until it emerges to a viable process which should be practical and economical. In the mean time, die level burn-in becomes a common method to produce KGD for its practical application as several different types of burn-in carriers are commercially available. In this paper, a new cost effective process to produce KGD is proposed. Conventional wire bonding method was applied for electrical interconnection from chip to printed circuit board, designed for testing several chip together with a multichip holder. A proprietary tool was applied to cut gold wire from bond pad. Mass production of KGD was possible with the new process. Engineering samples, I Meg slow static RAM, produced by the new process showed excellent reliability and provided a significant amount of engineering data. It is believed that the new process can produce known good bare die most economically among existing die level burn-in methods. Because it used well established wire bonding technology rather than burn-in carrier to provide temporary contact between chip to test equipment which quite often proved unreliable in terms of contact resistance and can be used only limited number of times.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127931931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0