Proceedings 20th Anniversary Conference on Advanced Research in VLSI最新文献_第3页

Who put the sugar in Sydney Harbor? [biosensors] 谁把糖扔进了悉尼港?(生物传感器)

Proceedings 20th Anniversary Conference on Advanced Research in VLSI Pub Date : 1999-03-21 DOI: 10.1109/ARVLSI.1999.756059

N. Weste

{"title":"Who put the sugar in Sydney Harbor? [biosensors]","authors":"N. Weste","doi":"10.1109/ARVLSI.1999.756059","DOIUrl":"https://doi.org/10.1109/ARVLSI.1999.756059","url":null,"abstract":"Summary form only given. Electronics and biology are being blended in many centers around the world to create new devices that interface with the real world (i.e. touch, smell and taste as well as sight and hearing). This talk will summarize the ongoing research work of AMBRI, the Australian Membrane and Biotechnology Research Institute to design and build unique, high sensitivity, biosensor technology utilizing ion channels as switches in a biological membrane. The basic cell delivers an acutely sensitive capsule, which measures biological concentrations of analytes electronically rather than photometrically. Quantities at sub-picomolar levels of concentration can be detected (i.e. a teaspoon of sugar in Sydney Harbor). The cell is a 'diagnostic laboratory', delivering the functionality of an expensive central laboratory to the field. To date, the cells have been built in isolation and connected to laboratory grade instrumentation. Macquarie University has designed a 96 element sensor chip that directly interfaces to an array of biosensors. The chip uses eight multiplexed sigma-delta converters to provide eight digital outputs that can digitize signals in the range of 1 to 1000 Hz at 12 bit resolution. This chip will enable an exciting new range of very small portable biological detectors to be fielded that can fill a myriad of applications. This talk summarizes the biosensor technology (from a non-expert point of view) and also describes the sensor chip that has been designed.","PeriodicalId":358015,"journal":{"name":"Proceedings 20th Anniversary Conference on Advanced Research in VLSI","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121125707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Area-universal circuits with constant slowdown 具有恒定减速的区域通用电路

Proceedings 20th Anniversary Conference on Advanced Research in VLSI Pub Date : 1999-03-21 DOI: 10.1109/ARVLSI.1999.756040

S. Bhatt, G. Bilardi, G. Pucci

{"title":"Area-universal circuits with constant slowdown","authors":"S. Bhatt, G. Bilardi, G. Pucci","doi":"10.1109/ARVLSI.1999.756040","DOIUrl":"https://doi.org/10.1109/ARVLSI.1999.756040","url":null,"abstract":"An area-universal VLSI circuit can be programmed to emulate every circuit of a given area, but at cost of lower area-time performance. In particular, if a circuit with area-time bounds (A,T) emulated with a universal circuit with bounds (A/sub u/,T/sub u/), we say that the universal circuit has slowup A/sub u//A and slowdown T/sub u//T. A central question in VLSI theory is to investigate the inherent costs and tradeoffs of universal circuit designs. Prior to this paper, universal designs with O(1) blowup and O(log A) slowdown for area-A circuits were known. Universal designs for area-A circuits of O(/spl radic/A/sup 1+/spl epsiv//logA) nodes, with O(A/sup /spl epsiv//) blowup and O(log log A) slowdown, had also been developed. However, the existence of universal circuits with O(1) slowdown and relatively small blowup was an open question. In this paper, we settle this question by designing an area-universal circuit U/sub A//sup /spl epsiv// with O(1//spl epsiv/) slowdown and O(/spl epsiv//sup 2/A/sup /spl epsiv// log/sup 4/A) blowup, for any value of the parameter /spl epsiv/, 1/log A/spl les//spl epsiv//spl les/1. By varying, we obtain universal circuits which operate at different points in the spectrum of the slowdown-slowup tradeoff. In particular, when /spl epsiv/ is chosen to be a constant, our universal circuit yields O(1) slowdown.","PeriodicalId":358015,"journal":{"name":"Proceedings 20th Anniversary Conference on Advanced Research in VLSI","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115178836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

The Ultrascalar processor-an asymptotically scalable superscalar microarchitecture 超标量处理器——渐近可扩展的超标量微体系结构

Proceedings 20th Anniversary Conference on Advanced Research in VLSI Pub Date : 1999-03-21 DOI: 10.1109/ARVLSI.1999.756053

Dana S. Henry, Bradley C. Kuszmaul, V. Viswanath

{"title":"The Ultrascalar processor-an asymptotically scalable superscalar microarchitecture","authors":"Dana S. Henry, Bradley C. Kuszmaul, V. Viswanath","doi":"10.1109/ARVLSI.1999.756053","DOIUrl":"https://doi.org/10.1109/ARVLSI.1999.756053","url":null,"abstract":"The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular the critical-path lengths of many components in existing implementations grow as /spl Theta/(n/sup 2/) where n is the fetch width, the issue width, or the window size. This paper presents a novel implementation, called the Ultrascalar processor, that dramatically reduces the asymptotic critical-path length of a superscalar processor. The processor is implemented by a large collection of ALUs with controllers (together called execution stations) connected together by a network of parallel-prefix tree circuits. A fat-tree network connects an interleaved cache to the execution stations. These networks provide the full functionality of superscalar processors including renaming, out-of-order execution, and speculative execution. The Ultrascalar's critical-path length due to gate delays is /spl tau//sub gates/=/spl Theta/(log n). The wire delays and chip size depend on the provided memory bandwidth and the layout. If the provided memory bandwidth is M(n) memory operations per clock cycle then, using an H-tree VLSI layout, the critical-path length due to wire delay (speed-of-light delay) is /spl tau//sub wires/={/spl Theta/(n/sup 1/2/) if M(n) is O(n/sup 1/2-/spl epsiv//) for /spl epsiv/>0, [optimal]; {/spl Theta/(n/sup 1/2/log n) if M(n) is /spl Theta/(n/sup 1/2/), [near optimal]; and {/spl Theta/(M(n)) if M(n) is /spl Omega/(n/sup 1/2+/spl epsiv//) for /spl epsiv/>0, [optimal] (with M suitably constrained.) The area is the square of the wire delay.","PeriodicalId":358015,"journal":{"name":"Proceedings 20th Anniversary Conference on Advanced Research in VLSI","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124052617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Low power gate resizing of combinational circuits by buffer-redistribution 利用缓冲再分配实现组合电路的低功率栅极调整

Proceedings 20th Anniversary Conference on Advanced Research in VLSI Pub Date : 1999-03-21 DOI: 10.1109/ARVLSI.1999.756047

V. Sundararajan, K. Parhi

{"title":"Low power gate resizing of combinational circuits by buffer-redistribution","authors":"V. Sundararajan, K. Parhi","doi":"10.1109/ARVLSI.1999.756047","DOIUrl":"https://doi.org/10.1109/ARVLSI.1999.756047","url":null,"abstract":"Low power gate resizing can decrease the power dissipated in a technology mapped circuit while maintaining its critical path. Gate resizing operates as a post-mapping technique for power reduction by replacing some gates, which are faster than necessary, with smaller and slower gates from the underlying gate library. In this paper we propose a new transformation technique for combinational circuits referred to as buffer-redistribution. Buffer-redistribution is then used to model and solve the low-power discrete gate resizing problem in an exact manner in polynomial time and in a noniterative fashion for a complete gate library. Suboptimal solutions are obtained with incomplete gate libraries. In contrast past polynomial time techniques for gate resizing were either based on heuristics or based on much slower iterative exact algorithms. Simulation results on ISCAS85 benchmark circuits demonstrate 2.1%-54.1% power reduction based on the proposed buffer-redistribution based low-power gate resizing. Power savings from 0%-44.13% are demonstrated over the same circuits mapped for minimum area. The time required for resizing varies from 2.77s-1256.76s.","PeriodicalId":358015,"journal":{"name":"Proceedings 20th Anniversary Conference on Advanced Research in VLSI","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128066784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Multi-chip neuromorphic motion processing 多芯片神经形态运动处理

Proceedings 20th Anniversary Conference on Advanced Research in VLSI Pub Date : 1999-03-21 DOI: 10.1109/ARVLSI.1999.756056

Charles M. Higgins, C. Koch

引用次数: 32

A quantitative approach to nonlinear process design rule scaling [VLSI] 非线性工艺设计规则缩放的定量方法[VLSI]

Proceedings 20th Anniversary Conference on Advanced Research in VLSI Pub Date : 1999-03-21 DOI: 10.1109/ARVLSI.1999.756041

S. M. Gold, Richard B. Brown, Bruce Bernhardt

{"title":"A quantitative approach to nonlinear process design rule scaling [VLSI]","authors":"S. M. Gold, Richard B. Brown, Bruce Bernhardt","doi":"10.1109/ARVLSI.1999.756041","DOIUrl":"https://doi.org/10.1109/ARVLSI.1999.756041","url":null,"abstract":"This paper describes a quantitative methodology for selecting nonlinear design rule scale factors that provide the most cost-efficient improvements in IC performance and area. The methodology includes identifying the design rules which have the greatest impact on the scaling objective and analyzing the area and performance improvements as these rules are scaled through a range of practical scale factors. Power and delay improvement data are then combined with die cost estimates to produce a cost/benefit ratio, a quantitative metric for design rule scaling cost-efficiency. The slopes and inflection points of cost/benefit vs. scale factor plots will guide process engineers in selecting scale factors for the various design rules. This procedure is repeated using the results of one iteration as the starting point for the next. The cost/benefit analysis methodology is demonstrated by comparing embedded static RAMs implemented in a complementary GaAs (CGaAs/sup TM/) process. The SRAMs are generated by a process-independent, optimizing SRAM compiler which can create SRAM macrocells for any complementary technology. A cost/benefit analysis of the CGaAs design rules shows that when operating under a fixed spending cap for process scaling research, development, and capital equipment acquisition, nonlinear scaling can provide greater improvements in area and performance than linear scaling. The results also show that for a 0.5 /spl mu/m CGaAs process to be fabricated in high volume, the first scaling step should be a 30% reduction of the source drain area and via/metal pitch, gate metal to ohmic spacing, and gate metal spacing design rules.","PeriodicalId":358015,"journal":{"name":"Proceedings 20th Anniversary Conference on Advanced Research in VLSI","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122910980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Battery-powered, wireless MEMS sensors for high-sensitivity chemical and biological sensing 电池供电的无线MEMS传感器，用于高灵敏度的化学和生物传感

Proceedings 20th Anniversary Conference on Advanced Research in VLSI Pub Date : 1999-03-21 DOI: 10.1109/ARVLSI.1999.756060

C. L. Britton, R. Warmack, Stephen F. Smith, P. I. Oden, R. L. Jones, T. Thundat, G. M. Brown, W. Bryan, J. Depriest, M. N. Ericson, M. Emery, Michael R. Moore, Gary W. Turner, A. Wintenberg, T. D. Threatt, Zhiyu Hu, L. Clonts, J. M. Rochelle

{"title":"Battery-powered, wireless MEMS sensors for high-sensitivity chemical and biological sensing","authors":"C. L. Britton, R. Warmack, Stephen F. Smith, P. I. Oden, R. L. Jones, T. Thundat, G. M. Brown, W. Bryan, J. Depriest, M. N. Ericson, M. Emery, Michael R. Moore, Gary W. Turner, A. Wintenberg, T. D. Threatt, Zhiyu Hu, L. Clonts, J. M. Rochelle","doi":"10.1109/ARVLSI.1999.756060","DOIUrl":"https://doi.org/10.1109/ARVLSI.1999.756060","url":null,"abstract":"Researchers at Oak Ridge National Laboratory (ORNL) are developing selectively coated cantilever arrays in a surface-micromachined MEMS process for very high sensitivities in chemical and biological sensing. Toward this end, we have developed a one-dimensional (1-D) 10-element microcantilever array that we have coated with gold for mercury sensing and palladium for hydrogen sensing. Ultimately we will coat each element with a different coating. Currently, measurements have been performed using a companion analog 1.2-/spl mu/m CMOS eight channel readout chip also designed at ORNL specifically for the microcantilever arrays. In addition, we have combined our sensors with an ORNL-developed RF-telemetry chip having on-chip spread spectrum encoding and modulation circuitry to improve the robustness and security of sensor data in typical interference- and multipath-impaired environments. We have also provided for a selection of distinct spreading codes to serve groups of sensors in a common environment by the application of code-division multiple-access techniques. Our initial system is configured for use in the 915-MHz Industrial, Scientific, and Medical (ISM) band. The entire package is powered by four AA batteries.","PeriodicalId":358015,"journal":{"name":"Proceedings 20th Anniversary Conference on Advanced Research in VLSI","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122037298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

XXI century gigascale integration (GSI): the interconnect problem 21世纪千兆级集成(GSI):互连问题

Proceedings 20th Anniversary Conference on Advanced Research in VLSI Pub Date : 1900-01-01 DOI: 10.1109/ARVLSI.1999.756039

J. Meindl

{"title":"XXI century gigascale integration (GSI): the interconnect problem","authors":"J. Meindl","doi":"10.1109/ARVLSI.1999.756039","DOIUrl":"https://doi.org/10.1109/ARVLSI.1999.756039","url":null,"abstract":"Summary form only given, as follows. From the inception of microelectronics in 1959 until the early 1990's, transistors dominated both the performance and cost of microchips while interconnects were of secondary importance. In recent years, this hegemony has reversed itself. Interconnects now tend to dominate microchip performance and cost with transistors relegated to the secondary role. As an example, for late 1980's 1.0 /spl mu/m technology, the intrinsic switching delay of an unloaded MOSFET approaches 10 ps while the response time of a 1.0 mm interconnect is approximately 1 ps. But, for early 2000's 0.1 /spl mu/m technology, the intrinsic delay of a MOSFET decreases to about 1.0 ps while the response time of a 1.0 mm interconnect increases to 100 ps. Concurrent with this signal wiring dilemma, clock frequency is increasing by 100X placing stringent new demands on the chip clock distribution network. Supply current is increasing by 60X while supply voltage scales downward by 5X thereby imposing a huge new burden on the power distribution network. Maximum total wire length per chip increases by 50X, while chip-to-package input-output interconnect count increases by 10X. The profound and pervasive nature of the interconnect problem demands a response. The central thesis of this response is that early XXI century opportunities for GSI will be governed by an interconnect dominated hierarchy of theoretical and practical limits whose five levels are codified as fundamental, material, device, circuit and system. Systematic exploration of this hierarchy of limits reveals salient opportunities for addressing the interconnect problem.","PeriodicalId":358015,"journal":{"name":"Proceedings 20th Anniversary Conference on Advanced Research in VLSI","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125422941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1