Proceedings 20th Anniversary Conference on Advanced Research in VLSI最新文献

Algorithms promoting the use of dual supply voltages for power-driven designs 在功率驱动设计中促进使用双电源电压的算法

Proceedings 20th Anniversary Conference on Advanced Research in VLSI Pub Date : 1999-03-21 DOI: 10.1109/ARVLSI.1999.756046

C. Yeh, Min-Cheng Chang, Yin-Shuin Kang

引用次数: 0

A two-dimensional, object-based analog VLSI visual attention system 一个二维的，基于对象的模拟VLSI视觉注意系统

Proceedings 20th Anniversary Conference on Advanced Research in VLSI Pub Date : 1999-03-21 DOI: 10.1109/ARVLSI.1999.756055

Charles S. Wilson, T. Morris, S. DeWeerth

引用次数: 15

VLSI architecture: past, present, and future VLSI架构:过去、现在和未来

Proceedings 20th Anniversary Conference on Advanced Research in VLSI Pub Date : 1999-03-21 DOI: 10.1109/ARVLSI.1999.756051

W. Dally, Steve Lacy

引用次数: 82

MEMS-based capacitor arrays for programmable interconnect and RF applications 用于可编程互连和射频应用的基于mems的电容器阵列

Proceedings 20th Anniversary Conference on Advanced Research in VLSI Pub Date : 1999-03-21 DOI: 10.1109/ARVLSI.1999.756061

B. Duewer, John M. Wilson, D. Winick, P. Franzon

引用次数: 4

Clock-powered CMOS: a hybrid adiabatic logic style for energy-efficient computing 时钟驱动的CMOS:用于节能计算的混合绝热逻辑风格

Proceedings 20th Anniversary Conference on Advanced Research in VLSI Pub Date : 1999-03-21 DOI: 10.1109/ARVLSI.1999.756044

N. Tzartzanis, W. Athas

{"title":"Clock-powered CMOS: a hybrid adiabatic logic style for energy-efficient computing","authors":"N. Tzartzanis, W. Athas","doi":"10.1109/ARVLSI.1999.756044","DOIUrl":"https://doi.org/10.1109/ARVLSI.1999.756044","url":null,"abstract":"Clock-powered logic is a new CMOS logic style which combines adiabatic switching and energy recovery-techniques with conventional CMOS logic styles for the design of low-power computing microsystems. In clock-powered logic high-capacitance nodes are adiabatically switched and powered from AC sources typically the clock lines. Low-capacitance nodes are conventionally switched and powered front a DC supply source. The clocked buffer, a CMOS structure based on bootstrapping, drives the high-capacitance nodes from the clock lines. An analytical model that closely estimates the on-resistance of the bootstrapped nFET is derived. The model is evaluated through H-SPICE simulations. Depending on the CMOS logic style used for the DC-powered blocks, pulse-to-level converters may be required to interface the clocked buffer outputs with the logic blocks. These converters inherently act as low-to-high voltage converters. Therefore, low-power operation can be achieved with clock-powered logic by both increasing the switching time and reducing the voltage swing of clock-powered nodes. This feature of clock-powered logic is evaluated through H-SPICE simulations in which the clocked buffer is compared with conventional supply-scaled CMOS drivers. The clocked buffer combined with adiabatic switching demonstrates superior energy vs. delay scalability than its supply-scaled counterparts.","PeriodicalId":358015,"journal":{"name":"Proceedings 20th Anniversary Conference on Advanced Research in VLSI","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122746468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

A column-based processing array for high-speed digital image processing 用于高速数字图像处理的基于列的处理阵列

Proceedings 20th Anniversary Conference on Advanced Research in VLSI Pub Date : 1999-03-21 DOI: 10.1109/ARVLSI.1999.756036

T. Morris, Erica Fletcher, Cyrus Afghahi, S. Issa, K. Connolly, Jean-Charles Korta

{"title":"A column-based processing array for high-speed digital image processing","authors":"T. Morris, Erica Fletcher, Cyrus Afghahi, S. Issa, K. Connolly, Jean-Charles Korta","doi":"10.1109/ARVLSI.1999.756036","DOIUrl":"https://doi.org/10.1109/ARVLSI.1999.756036","url":null,"abstract":"We present a novel architecture for column-based image processing within an integrated CMOS sensor chip. The system includes a two-dimensional array of active pixel sensors, a one-dimensional array of analog-to-digital converters along one side of the sensor array, an array of static random access memory (SRAM) cells, and a one-dimensional array of parallel digital processing units. The architecture offers much potential for scalability, primarily due to a rotation of the digital bits coming out of the analog-to-digital converter. Each data converter produces an 8-bit value, which is then stored horizontally in an SRAM byte extending across 8 columns of pixels. This arrangement of data enables 8-bit parallel processing by each of the arithmetic logic units (ALUs), which also extends along 8 pixel columns. This grouping of 8 columns is referred to as a block-column. We describe the architecture and discuss implementation issues encountered during the design of two separate test devices fabricated in a 0.35 /spl mu/m digital CMOS process. We also present results of an architectural analysis with example algorithms.","PeriodicalId":358015,"journal":{"name":"Proceedings 20th Anniversary Conference on Advanced Research in VLSI","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131568037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Noise margin constraints for interconnectivity in deep submicron low power and mixed-signal VLSI circuits 深亚微米低功耗和混合信号VLSI电路互连的噪声裕度约束

Proceedings 20th Anniversary Conference on Advanced Research in VLSI Pub Date : 1999-03-21 DOI: 10.1109/ARVLSI.1999.756043

Lirong Zheng, H. Tenhunen

{"title":"Noise margin constraints for interconnectivity in deep submicron low power and mixed-signal VLSI circuits","authors":"Lirong Zheng, H. Tenhunen","doi":"10.1109/ARVLSI.1999.756043","DOIUrl":"https://doi.org/10.1109/ARVLSI.1999.756043","url":null,"abstract":"The continually growth in density and complexity of integrated circuits gives a difficult challenge in wireability of deep submicron VLSI circuits, particularly the advanced low power and mixed-signal ICs, where the interconnections have been seriously limited by the noise coupling problem. In this paper, we analyse the interconnectivity of advanced deep submicron low power and mixed-signal VLSI circuits under noise margin constraints. We show that noise margin constraint for signal coupling will restrict interconnect density as well as process technology options. The maximum interconnectivity, process technology options, and physical delay etc. are analysed against the noise margin constraints, for both with and without shielding wire cases. The optimal geometry and wirings for both local and global interconnects are studied with respect to noise margin, physical delay, and interconnect cross section area etc. Constraint for maximum available interconnectivity is demonstrated for interconnect wire geometry characteristics of advanced deep submicron CMOS processes. Our study reveals that, in advanced deep submicron VLSI circuit designs, interconnects should be separated functionally. Different geometries and wiring types and perhaps different fabrication flows and processes should be utilized in one chip. Some of the interconnect layers will be thus heavily dedicated such as some for local interconnects, some for intramodule interconnects, some for global wiring, and some for ground and power etc., all with optimal geometries.","PeriodicalId":358015,"journal":{"name":"Proceedings 20th Anniversary Conference on Advanced Research in VLSI","volume":"363 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115079175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Interconnect-dominated VLSI design 互连为主的VLSI设计

Proceedings 20th Anniversary Conference on Advanced Research in VLSI Pub Date : 1999-03-21 DOI: 10.1109/ARVLSI.1999.756042

P. Ghosh, R. Mangaser, C. Mark, K. Rose

引用次数: 15

Translinear analog signal processing: a modular approach to large-scale analog computation with multiple-input translinear elements 跨线性模拟信号处理:多输入跨线性元素大规模模拟计算的模块化方法

Proceedings 20th Anniversary Conference on Advanced Research in VLSI Pub Date : 1999-03-21 DOI: 10.1109/ARVLSI.1999.756048

B. Minch

{"title":"Translinear analog signal processing: a modular approach to large-scale analog computation with multiple-input translinear elements","authors":"B. Minch","doi":"10.1109/ARVLSI.1999.756048","DOIUrl":"https://doi.org/10.1109/ARVLSI.1999.756048","url":null,"abstract":"The author describes a general framework, called translinear analog signal processing (TASP), for implementing continuous-time analog signal processing systems that have a wide dynamic range and can operate with a low power-supply voltage. Such analog signal processing systems are highly modular, comprising only grounded capacitors, constant current sources, and simple circuit primitives called multiple-input translinear elements (MITEs). Moreover, the behavior of a TASP system is well described in terms of commonly used linear and nonlinear signal processing functions. Consequently, these systems should be highly amenable to behavioral-level descriptions and to computer-aided design automation techniques. The author briefly discusses the operation of MITEs and their circuit implementation. He describes the two classes of MITE circuits, MITE networks and MITE log-domain filters, that together make up the TASP framework and shows experimental data from a basic circuit from each class. The author then illustrates how we can interface these circuits in a seamless fashion to build large-scale TASP systems. Finally, he discuss the possibility of building adaptive and reconfigurable TASP systems.","PeriodicalId":358015,"journal":{"name":"Proceedings 20th Anniversary Conference on Advanced Research in VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126840981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Feedback driven backtrace of analog signals and its application to circuit verification and test 模拟信号的反馈驱动回溯及其在电路验证和测试中的应用

Proceedings 20th Anniversary Conference on Advanced Research in VLSI Pub Date : 1999-03-21 DOI: 10.1109/ARVLSI.1999.756058

R. Voorakaranam, A. Chatterjee

引用次数: 7