Proceedings 20th Anniversary Conference on Advanced Research in VLSI最新文献

{"title":"Impact of power density limitation in gigascale integration for the SIMD pixel processor","authors":"S. Chai, A. Gentile, D. S. Wills","doi":"10.1109/ARVLSI.1999.756037","DOIUrl":"https://doi.org/10.1109/ARVLSI.1999.756037","url":null,"abstract":"Gigascale Integration (GSI) enables a new generation of monolithic focal plane processing systems built with billion-transistor chips. As this technology matures, fundamental technology limitations on wire interconnects and power dissipation will become the performance bottleneck. This paper presents system performance projections for GSI technologies under these constraints. Architectural models and workload characterization are integrated to identify viable future system implementations. The SIMD Pixel processor (SIMPil) is selected as the architecture for evaluation, and an image processing application suite is programmed to characterize the workload. Projections for SIMPil systems show that over three orders of magnitude improvement is achievable by 2012 in both system throughput and image resolution. System power consumption is contained below 50 W for a 52,900 processor system in 50 nm technology. The SIMPil architecture design space is explored, and opportunities for more aggressive designs within power density limits are examined.","PeriodicalId":358015,"journal":{"name":"Proceedings 20th Anniversary Conference on Advanced Research in VLSI","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131555957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimal clocking and enhanced testability for high-performance self-resetting domino pipelines","authors":"Ayoob E. Dooply, K. Yun","doi":"10.1109/ARVLSI.1999.756049","DOIUrl":"https://doi.org/10.1109/ARVLSI.1999.756049","url":null,"abstract":"We describe a method to clock the domino pipeline at the maximum rate by using soft synchronizers between pipeline stages and thus allowing \"time borrowing\" i.e., allowing input signals to arrive at a pipe stage after the clock tick. We show a robust way of placing \"roadblocks\" (equivalent to slave latches) in each pipe stage to maintain the optimal clock rate. As explicit latches are not required at the pipe stage boundaries, the latch overhead is eliminated. We use the self-resetting scheme to circumvent often performance-limiting precharge timing requirements. We also address several issues regarding the testability of self-resetting domino circuits including scan register design and multiple stuck fault testing.","PeriodicalId":358015,"journal":{"name":"Proceedings 20th Anniversary Conference on Advanced Research in VLSI","volume":"178 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134160396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Conjunction search using a 1-D, analog VLSI-based, attentional search/tracking chip","authors":"T. Horiuchi, E. Niebur","doi":"10.1109/ARVLSI.1999.756054","DOIUrl":"https://doi.org/10.1109/ARVLSI.1999.756054","url":null,"abstract":"The ability of animals to select a limited region of sensory space for scrutiny is an important factor in dealing with cluttered or complex sensory environments. Such an \"attentional\" system in the visual domain is believed to be involved in both the perception of objects and the control of eye movements in primates. While we can intentionally guide our attention to perform a specific task, it is also reflexively drawn to \"salient\" features in our sensory input space. Understanding how high-level task information and lour-level stimulus information can combine to control our sensory processing is of great interest to both neuroscience and engineering. Towards this end, we have designed and fabricated a one-dimensional, analog VLSI vision chip that models covert attentional search and tracking. We extend previous analog VLSI work (Morris and DeWeerth, 1997) on the delayed onset of inhibition in a winner-take-all network to now use extracted image edges as input to the attentional saliency map and to perform serial search on a particular feature conjunction (spatial derivative and the direction-of-motion). We further demonstrate the ability to modify the circuit's parameters \"on-the-fly\" to switch between a search mode and a tracking mode.","PeriodicalId":358015,"journal":{"name":"Proceedings 20th Anniversary Conference on Advanced Research in VLSI","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134633362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Compact fault dictionary construction for efficient isolation of faults in analog and mixed-signal circuits","authors":"S. Chakrabarti, A. Chatterjee","doi":"10.1109/ARVLSI.1999.756057","DOIUrl":"https://doi.org/10.1109/ARVLSI.1999.756057","url":null,"abstract":"Diverse design styles and the associated complex circuit specifications make testing by functional methods prohibitively expensive for most analog and mixed-signal circuits. Hence, fault oriented test techniques, similar to those for digital circuits, are being actively pursued in the research community. However the large number of failure mechanisms in analog and mixed-signal circuits presents a major bottleneck in terms of fault simulation effort and in the construction of compact fault dictionaries. In this paper, we propose an efficient fault sampling and clustering methodology to construct compact fault dictionaries for complex analog and mixed-signal circuits, with significantly reduced fault simulation effort. For a given fault universe, we show that only a small fraction of the total faults need to be simulated and stored in the fault dictionary to achieve near-perfect diagnosis. A fault sampling algorithm is proposed to identify the faults that contribute to diagnostic information with minimal simulation effort. A fault clustering algorithm is applied to the resulting fault syndromes to identify equivalent syndromes with maximal diagnostic information content. For complex analog/mixed-signal circuits, the fault sampling and fault clustering algorithms are applied hierarchically to construct the compact fault dictionaries, without sacrificing diagnostic accuracy.","PeriodicalId":358015,"journal":{"name":"Proceedings 20th Anniversary Conference on Advanced Research in VLSI","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122652500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"System-on-a-chip VLSI-is it finally really here?","authors":"R. Brodersen","doi":"10.1109/ARVLSI.1999.756045","DOIUrl":"https://doi.org/10.1109/ARVLSI.1999.756045","url":null,"abstract":"Summary form only given. System-on-a-chip VLSI has long been discussed and has many meanings, with the most compelling being a design which has components at a level above what is presently being used. In the past this has sometimes simply been a heterogeneous design which simultaneously includes either analog with digital or non-transistor structures or even simply just different kinds of digital circuitry. While all of these have design challenges beyond that necessary for a single type, it is the possible inclusion of all the above (analog, non-transistor, various types of digital) which rises to the level of a true system-on-a-chip. This represents the integration of all the functions which were previously interconnected on a PC board or boards, which is one level higher than what has been previously possible. Such high levels of integration are required in those applications which are cost, power and size sensitive and the most clear example of such products are systems which wireless communications in portable devices. This can range from cell phones to portable multimedia terminals and demonstrations of these systems are now beginning to appear which have integration of both the analog and digital functions as well as passive elements that are compatible with CMOS. These prototypical system-on-a-chip implementations are further complicated by the various types of digital computation which are required. The demand for the most efficient integrated solution requires a simultaneous optimization of the passive devices, analog circuits as well as the computational structures used to implement the digital processing. The choice of the latter is particularly important as the various approaches can range over many orders of magnitude in size and energy efficiency. The design of portable wireless systems is particularly rich in that it not only involves the circuit design, but a number of other fields including communication theory, radio architecture, RF analog design and software. It is the possibility of integration of circuit structures that support these highly diverse areas that results in the conclusion that system-on-chip VLSI has finally arrived.","PeriodicalId":358015,"journal":{"name":"Proceedings 20th Anniversary Conference on Advanced Research in VLSI","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115028456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Architecture design of reconfigurable pipelined datapaths","authors":"Darren C. Cronquist, C. Fisher, M. Figueroa, Paul Franklin, C. Ebeling","doi":"10.1109/ARVLSI.1999.756035","DOIUrl":"https://doi.org/10.1109/ARVLSI.1999.756035","url":null,"abstract":"This paper examines reconfigurable pipelined datapaths (RaPiDs), a new architecture style for computation-intensive applications that bridges the cost/performance gap between general purpose and application specific architectures. RaPiDs can provide significantly higher performance than general purpose processors on a wide range of applications from the areas of video and signal processing, scientific computing and communications. Moreover, RaPiDs provide the flexibility that does not come with application-specific architectures. A RaPiD architecture is optimized for highly repetitive, computationally-intensive tasks. Very deep application-specific computation pipelines can be configured that deliver very high performance for a wide range of applications. RaPiDs achieve this using a coarse-grained reconfigurable architecture that mixes the appropriate amount of static configuration with dynamic control. We describe the fundamental features of a RaPiD architecture, including the linear array of functional units, a programmable segmented bus structure, and a programmable control architecture. In addition, we outline the floorplan of the architecture and provide timing data for the most critical paths. We conclude with performance numbers for several applications on an instance of a RaPiD architecture.","PeriodicalId":358015,"journal":{"name":"Proceedings 20th Anniversary Conference on Advanced Research in VLSI","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132592982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Problems and prospects for electrical signaling [VLSI]","authors":"J. Poulton","doi":"10.1109/ARVLSI.1999.833402","DOIUrl":"https://doi.org/10.1109/ARVLSI.1999.833402","url":null,"abstract":"Summary form only given, as follows. The growing gap between on-chip gates and off-chip I/O bandwidth is reaching crisis proportions, yet signaling system designers continue to use inefficient and inappropriate circuit techniques for many chip-to-chip interconnections. For example, most chip-to-chip interconnect still uses CMOS inverters as transmitters and receivers, even though it would be difficult to imagine more unfavorable components for a signaling system. Processor-to-memory and processor-to-processor communication systems are still almost universally built using physical buses, transmission lines with multiple loads attached along their length. Though logically simple and convenient, these structures impose fundamental limits on signal speed that preclude their use above about 1-2 Gbaud, exact a heavy price in power dissipation, and are very difficult to engineer. Some have suggested replacing electrical signaling with optical interconnect; however, converting between optical and electrical signals is still expensive, and in any case, electrical signaling is far from its theoretical limits. With reasonable assumptions, the wiring embedded in a typical circuit board has bisection bandwidth of order 10 s of Tbit/s. Recent advances in high-speed serial link techniques point the way to unlocking a substantial fraction of this bandwidth. In CMOS, 1-2 Gbit/s links are fairly common, experimental 4 Gb/sec links have been demonstrated, and speeds up to 20 Gbits/s appear quite feasible.","PeriodicalId":358015,"journal":{"name":"Proceedings 20th Anniversary Conference on Advanced Research in VLSI","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129392309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A throughput-on-demand address-event transmitter for neuromorphic chips","authors":"K. Boahen","doi":"10.1109/ARVLSI.1999.756038","DOIUrl":"https://doi.org/10.1109/ARVLSI.1999.756038","url":null,"abstract":"The author presents a scalable 2D address-event transmitter interface designed to take advantage of the high integration densities available with advanced submicron technology. To sustain throughput, it exploits the linear increase in the number of active neurons per row with array size, instead of counting on a linear increase in the unit-current/unit-capacitance ratio, as existing designs do. The author synthesizes an asynchronous implementation starting from a high-level specification, and presents test results from a 104/spl times/96-neuron chip fabricated in a 1.2 /spl mu/m CMOS process. Reading out the state of all neurons in a selected row in parallel, and sending their spikes in a tight burst of events, yields cycle times between 40 to 70 ns-six to ten times shorter than the 420 ns minimum cycle time reported in earlier work.","PeriodicalId":358015,"journal":{"name":"Proceedings 20th Anniversary Conference on Advanced Research in VLSI","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132705888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Architectural considerations for application-specific counterflow pipelines","authors":"B. Childers, J. Davidson","doi":"10.1109/ARVLSI.1999.756034","DOIUrl":"https://doi.org/10.1109/ARVLSI.1999.756034","url":null,"abstract":"Application-specific processor design is a promising approach for meeting the performance and cost goals of a system. Application-specific processors are especially promising for embedded systems (e.g., digital cameras, cellular phones, etc.) where a small increase in performance and decrease in cost can have a large impact on a product's viability. Sproull, Sutherland and Molnar (see IEEE Design and Test of Computers, vol. 11, no. 3, p. 48-59, 1994) have proposed a new pipeline organization called the Counterflow Pipeline (CFP). This paper evaluates CFP design alternatives and shows that the CFP is an ideal architecture for fast, low-cost design of high-performance processors customized for computation-intensive embedded applications. First, we describe why CFP's are particularly well-suited to realizing application-specific processors. Second we describe how a CFP tailored to an application can be constructed automatically. Third, we present measurements that evaluate CFP design trade-offs and show that CFP's provide speculative and out-of-order execution, and register renaming that is matched to an application. Fourth, we show that asynchronous counterflow pipelines achieve high-performance by reducing the average execution latency of instructions over synchronous implementations. Finally, we demonstrate that custom CFP's achieve cycles per instruction measurements that are competitive with 4-way superscalar out-of-order processors at a potentially low design complexity.","PeriodicalId":358015,"journal":{"name":"Proceedings 20th Anniversary Conference on Advanced Research in VLSI","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125858875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Adaptive circuits using pFET floating-gate devices","authors":"P. Hasler, B. Minch, C. Diorio","doi":"10.1109/ARVLSI.1999.756050","DOIUrl":"https://doi.org/10.1109/ARVLSI.1999.756050","url":null,"abstract":"In this paper, we describe our floating-gate pFET device, with its many circuit applications and supporting experimental measurements. We developed these devices in standard double-poly CMOS technologies by utilizing many effects inherent in these processes. We add floating-gate charge by electron tunneling, and we remove floating-gate charge by hot-electron injection. With this floating-gate technology, we cannot only build analog EEPROMs, we can also implement adaptation and learning when we consider floating-gate devices to be circuit elements with important time-domain dynamics. We start by discussing non-adaptive properties of floating-gate devices and we present two representative non-adaptive applications. First, we discuss using the floating-gate pFETs as non-volatile voltage sources or potentiometers (e-pots). Second, we discuss using floating-gate pFETs to build translinear circuits that compute the product of powers of the input currents. We then discuss the physics, behavior, and applications of adaptation using floating-gate pFETs. The physics of adaptation starts with floating-gate pFETs with continuous tunneling and injection currents. A single floating-gate MOS device operating with continuous-time tunneling and injection currents can exhibit either stabilizing or destabilizing behaviors. One particular application is an autozeroing floating-gate amplifier (AFGA) that uses tunneling and pFET hot-electron injection to adaptively set its DC operating point. Continuous-time circuits comprising multiple floating-gate MOS devices show various competitive and cooperative behaviors between devices. These floating-gate circuits can be used to build silicon systems that adapt and learn.","PeriodicalId":358015,"journal":{"name":"Proceedings 20th Anniversary Conference on Advanced Research in VLSI","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132944070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}