{"title":"时钟驱动的CMOS:用于节能计算的混合绝热逻辑风格","authors":"N. Tzartzanis, W. Athas","doi":"10.1109/ARVLSI.1999.756044","DOIUrl":null,"url":null,"abstract":"Clock-powered logic is a new CMOS logic style which combines adiabatic switching and energy recovery-techniques with conventional CMOS logic styles for the design of low-power computing microsystems. In clock-powered logic high-capacitance nodes are adiabatically switched and powered from AC sources typically the clock lines. Low-capacitance nodes are conventionally switched and powered front a DC supply source. The clocked buffer, a CMOS structure based on bootstrapping, drives the high-capacitance nodes from the clock lines. An analytical model that closely estimates the on-resistance of the bootstrapped nFET is derived. The model is evaluated through H-SPICE simulations. Depending on the CMOS logic style used for the DC-powered blocks, pulse-to-level converters may be required to interface the clocked buffer outputs with the logic blocks. These converters inherently act as low-to-high voltage converters. Therefore, low-power operation can be achieved with clock-powered logic by both increasing the switching time and reducing the voltage swing of clock-powered nodes. This feature of clock-powered logic is evaluated through H-SPICE simulations in which the clocked buffer is compared with conventional supply-scaled CMOS drivers. The clocked buffer combined with adiabatic switching demonstrates superior energy vs. delay scalability than its supply-scaled counterparts.","PeriodicalId":358015,"journal":{"name":"Proceedings 20th Anniversary Conference on Advanced Research in VLSI","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Clock-powered CMOS: a hybrid adiabatic logic style for energy-efficient computing\",\"authors\":\"N. Tzartzanis, W. Athas\",\"doi\":\"10.1109/ARVLSI.1999.756044\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Clock-powered logic is a new CMOS logic style which combines adiabatic switching and energy recovery-techniques with conventional CMOS logic styles for the design of low-power computing microsystems. In clock-powered logic high-capacitance nodes are adiabatically switched and powered from AC sources typically the clock lines. Low-capacitance nodes are conventionally switched and powered front a DC supply source. The clocked buffer, a CMOS structure based on bootstrapping, drives the high-capacitance nodes from the clock lines. An analytical model that closely estimates the on-resistance of the bootstrapped nFET is derived. The model is evaluated through H-SPICE simulations. Depending on the CMOS logic style used for the DC-powered blocks, pulse-to-level converters may be required to interface the clocked buffer outputs with the logic blocks. These converters inherently act as low-to-high voltage converters. Therefore, low-power operation can be achieved with clock-powered logic by both increasing the switching time and reducing the voltage swing of clock-powered nodes. This feature of clock-powered logic is evaluated through H-SPICE simulations in which the clocked buffer is compared with conventional supply-scaled CMOS drivers. The clocked buffer combined with adiabatic switching demonstrates superior energy vs. delay scalability than its supply-scaled counterparts.\",\"PeriodicalId\":358015,\"journal\":{\"name\":\"Proceedings 20th Anniversary Conference on Advanced Research in VLSI\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-03-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 20th Anniversary Conference on Advanced Research in VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ARVLSI.1999.756044\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 20th Anniversary Conference on Advanced Research in VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARVLSI.1999.756044","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Clock-powered CMOS: a hybrid adiabatic logic style for energy-efficient computing
Clock-powered logic is a new CMOS logic style which combines adiabatic switching and energy recovery-techniques with conventional CMOS logic styles for the design of low-power computing microsystems. In clock-powered logic high-capacitance nodes are adiabatically switched and powered from AC sources typically the clock lines. Low-capacitance nodes are conventionally switched and powered front a DC supply source. The clocked buffer, a CMOS structure based on bootstrapping, drives the high-capacitance nodes from the clock lines. An analytical model that closely estimates the on-resistance of the bootstrapped nFET is derived. The model is evaluated through H-SPICE simulations. Depending on the CMOS logic style used for the DC-powered blocks, pulse-to-level converters may be required to interface the clocked buffer outputs with the logic blocks. These converters inherently act as low-to-high voltage converters. Therefore, low-power operation can be achieved with clock-powered logic by both increasing the switching time and reducing the voltage swing of clock-powered nodes. This feature of clock-powered logic is evaluated through H-SPICE simulations in which the clocked buffer is compared with conventional supply-scaled CMOS drivers. The clocked buffer combined with adiabatic switching demonstrates superior energy vs. delay scalability than its supply-scaled counterparts.