Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.最新文献_第5页

A 0.75-mW analog processor IC for wireless biosignal monitor 一种用于无线生物信号监测的0.75 mw模拟处理器IC

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1145/871506.871616

Chih-Jen Yen, Mely Chen Chi, Danny Wen-Yaw Chung, Shing-Hao Lee

引用次数: 6

Estimating influence of data layout optimizations on SDRAM energy consumption 估计数据布局优化对SDRAM能耗的影响

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1145/871506.871520

Hyun Suk Kim, N. Vijaykrishnan, M. Kandemir, E. Brockmeyer, F. Catthoor, M. J. Irwin

引用次数: 20

Reverse-order source/drain formation with double offset spacer (RODOS) for CMOS low-power, high-speed and low-noise amplifiers 具有双偏置间隔(RODOS)的CMOS低功耗，高速和低噪声放大器的反序源漏形成

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1109/LPE.2003.1231860

W. Choi, J. Lee, Byung-Gook Park

引用次数: 0

Energy characterization of a tiled architecture processor with on-chip networks 片上网络平铺结构处理器的能量表征

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1145/871506.871610

J. Kim, M. Taylor, Jason E. Miller, D. Wentzlaff

引用次数: 143

A low-power VLSI architecture for turbo decoding turbo译码的低功耗VLSI架构

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1145/871506.871599

Seok-Jun Lee, Naresh R Shanbhag, A. Singer

引用次数: 17

Routine based OS-aware microprocessor resource adaptation for run-time operating system power saving 基于例程的操作系统感知微处理器资源适配，实现运行时操作系统节能

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1145/871506.871565

Tao Li, L. John

引用次数: 9

An ASIC design methodology with predictably low leakage, using leakage-immune standard cells 一种ASIC设计方法，具有可预测的低泄漏，使用泄漏免疫标准细胞

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1145/871506.871539

N. Jayakumar, S. Khatri

{"title":"An ASIC design methodology with predictably low leakage, using leakage-immune standard cells","authors":"N. Jayakumar, S. Khatri","doi":"10.1145/871506.871539","DOIUrl":"https://doi.org/10.1145/871506.871539","url":null,"abstract":"In this paper we introduce a low-leakage standard cell based ASIC design methodology which is based on the use of modified standard cells. These cells are designed to consume extremely low and predictable leakage currents in standby mode. For each cell in a standard cell library, we design two low-leakage variants of the cell. If the inputs of a cell during the standby mode of operation are such that the output has a high value, we minimize the leakage in the pull-down network, and vice versa. While technology mapping a circuit, we determine the particular variant to utilize in each instance, so as to minimize leakage of the final mapped design. We have designed and laid out our modified standard cells, and have performed experiments to compare placed-and-routed area, leakage and delays of our method against MTCMOS and a straightforward ASIC flow. Each design style we compare utilizes the same base standard cell library. Our results show that designs obtained using our methodology have better speed and area characteristics than designs implemented in MTCMOS. The exact leakage current obtained for MTCMOS is highly unpredictable, while our method exhibits leakage currents which are precisely estimable. The leakage current for HL designs can be dramatically lower than the worst-case leakage of MTCMOS based designs, and two orders of magnitude compared to traditional standard cells. Also, a design implemented in MTCMOS would require the use of separate power and ground supplies for latches and combinational logic, while our methodology does away with such a requirement.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130473669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Strained-Si devices and circuits for low-power applications 用于低功耗应用的应变硅器件和电路

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1109/LPE.2003.1231858

Keunwoo Kim, R. Joshi, C. Chuang

引用次数: 7

Exploiting program hotspots and code sequentiality for instruction cache leakage management 利用程序热点和代码顺序进行指令缓存泄漏管理

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1145/871506.871606

Jie S. Hu, A. Nadgir, N. Vijaykrishnan, M. J. Irwin, M. Kandemir

{"title":"Exploiting program hotspots and code sequentiality for instruction cache leakage management","authors":"Jie S. Hu, A. Nadgir, N. Vijaykrishnan, M. J. Irwin, M. Kandemir","doi":"10.1145/871506.871606","DOIUrl":"https://doi.org/10.1145/871506.871606","url":null,"abstract":"Leakage energy optimization for caches has been the target of much recent effort. In this work, we focus on instruction caches and tailor two techniques that exploit the two major factors that shape the instruction access behavior, namely, hotspot execution and sequentiality. First, we adopt a hotspot detection mechanism by profiling the branch behavior at runtime and utilize this to implement a HotSpot based Leakage Management (HSLM) mechanism. Second, we exploit code sequentiality in implementing a Just-InTime Activation (JITA) that transitions cache lines to active mode just before they are accessed.,We utilize the recently proposed drowsy cache that dynamically scales voltages for leakage reduction and implement various schemes that use different combinations of HSLM and JITA. Our experimental evaluation using the SPEC2000 benchmark suite shows that instruction cache leakage energy consumption can be reduced by 63%, 49% and 29%; on the average, as compared to an unoptimized cache, a recently proposed hardware optimized cache, and a cache optimized using compiler, respectively. Further, we observe that these energy savings can be obtained without a significant impact on performance.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128147186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 42

Reducing energy and delay using efficient victim caches 使用有效的受害者缓存减少能量和延迟

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1109/LPE.2003.1231873

G. Memik, Glenn D. Reinman, W. Mangione-Smith

引用次数: 24