Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.最新文献_第6页

Full chip leakage-estimation considering power supply and temperature variations 考虑电源和温度变化的全芯片泄漏估计

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1145/871506.871529

Haihua Su, Frank Liu, A. Devgan, E. Acar, S. Nassif

引用次数: 247

A systems approach to molecular electronics 分子电子学的系统方法

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1145/871506.871596

J. Heath

引用次数: 0

Electric-energy generation using variable-capacitive resonator for power-free LSI: efficiency analysis and fundamental experiment 无电大规模集成电路用变容谐振器发电效率分析及基础实验

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1109/LPE.2003.1231861

M. Miyazaki, Hidetoshi Tanaka, G. Ono, T. Nagano, N. Ohkubo, T. Kawahara, K. Yano

{"title":"Electric-energy generation using variable-capacitive resonator for power-free LSI: efficiency analysis and fundamental experiment","authors":"M. Miyazaki, Hidetoshi Tanaka, G. Ono, T. Nagano, N. Ohkubo, T. Kawahara, K. Yano","doi":"10.1109/LPE.2003.1231861","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231861","url":null,"abstract":"A power generator based on a vibration-to-electric energy converter using a variable-resonating capacitor is experimentally demonstrated. The generator consists of a complete system with a mechanical variable capacitor, a charge-transporting LC tank circuit and an externally powered timing-capture controller. A practical design methodology to maximize the efficiency of the vibration-to-electric energy generation system is also described. The efficiency of the generator is estimated based on three factors: the mechanical-energy loss, the charge-transportation loss, and the timing-capture loss. Through the mechanical-energy analysis, the optimum condition for the resonance is found. The parasitic elements in the charge transporter and the timing management of the capture scheme dominate the generation efficiency. These analyses enable the optimum design of the energy-generation system. An experimentally fabricated and measured generator theoretically has a maximum power of 580 nW; the measured power is 120 nW, so conversion efficiency is 21%. This results from a 43% mechanical energy loss and a 63% charge-transportation loss. The timing-capture scheme is manually determined and externally powered in the experiment, so its efficiency is not considered. With our result, a new system LSI application with an embedded power source can be explored for the ubiquitous computing era.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121134509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 95

Exploiting compiler-generated schedules for energy savings in high-performance processors 利用编译器生成的调度来节省高性能处理器的能源

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1145/871506.871608

M. Valluri, L. John, H. Hanson

引用次数: 13

Simultaneous Vt selection and assignment for leakage optimization 泄漏优化的同步Vt选择和分配

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1145/871506.871543

Ankur Srivastava

引用次数: 46

Energy-efficient data scrambling on memory-processor interfaces 内存处理器接口上的高能效数据置乱

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1145/871506.871517

L. Benini, A. Galati, A. Macii, E. Macii, M. Poncino

引用次数: 18

Power-aware scheduling of conditional task graphs in real-time multiprocessor systems 实时多处理器系统中条件任务图的功率感知调度

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1145/871506.871607

Dongkun Shin, Jihong Kim

引用次数: 78

Microprocessor pipeline energy analysis 微处理器管道能量分析

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1145/871506.871577

Karthikeyan Natarajan, H. Hanson, S. Keckler, C. R. Moore, D. Burger

引用次数: 24

Elements of low power design for integrated systems 集成系统的低功耗设计要素

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1145/871506.871558

S. Kang

引用次数: 32

Reducing reorder buffer complexity through selective operand caching 通过选择性操作数缓存减少重排序缓冲区的复杂性

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1145/871506.871564

Gürhan Küçük, D. Ponomarev, O. Ergin, K. Ghose

{"title":"Reducing reorder buffer complexity through selective operand caching","authors":"Gürhan Küçük, D. Ponomarev, O. Ergin, K. Ghose","doi":"10.1145/871506.871564","DOIUrl":"https://doi.org/10.1145/871506.871564","url":null,"abstract":"Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In some microarchitectures, such as the Intel P6, the ROB also serves as a repository for the uncommitted results. In these designs, the ROB is a complex multi-ported structure that dissipates a significant percentage of the overall chip power. Recently, a mechanism was introduced for reducing the ROB complexity and its power dissipation through the complete elimination of read ports for reading out source operands. The resulting performance degradation is countered by caching the most recently produced results in a small set of associatively-addressed latches (\"retention latches\"). We propose an enhancement to the above technique by leveraging the notion of short-lived operands (values targeting the registers that are renamed by the time the instruction producing the value reaches the writeback stage). As much as 87% of all generated values are short lived for the SPEC 2000 benchmarks. Significant improvements in the Utilization of retention latches, the overall performance, complexity and power are achieved by not caching short-lived values in the retention latches. As few as two retention latches allow all source operand read ports on the ROB to be completely eliminated with very little impact on performance.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128055183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 117