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Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.最新文献

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ISLPED'03. Proceedings of the 2003 International Symposium on Low Power Electronics and Design (IEEE Cat. No.03TH8713) ISLPED 03。2003年国际低功耗电子与设计研讨会论文集(IEEE Cat)。No.03TH8713)
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 1900-01-01 DOI: 10.1109/LPE.2003.1231820
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引用次数: 0
Checkpointing alternatives for high-performance, power-aware processors 高性能、功率感知处理器的检查点替代方案
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 1900-01-01 DOI: 10.1109/LPE.2003.1231886
A. Moshovos
{"title":"Checkpointing alternatives for high-performance, power-aware processors","authors":"A. Moshovos","doi":"10.1109/LPE.2003.1231886","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231886","url":null,"abstract":"High performance processors use checkpointing to rapidly recover from branch mispredictions and possibly other exceptions. We demonstrate that conventional checkpointing becomes unattractive in terms of resource and power requirements for future generation processors. We propose out-of-order checkpoint release and checkpoint prediction, two alternatives that require significantly less resources and power while maintaining high-performance. We demonstrate their utility at the register alias table (RAT). Our methods reduce the number of RAT checkpoints to 1/3 (from 48 down to 16) for an aggressive, 8-way superscalar processor with a 256-entry instruction window. Using a 0.18 /spl mu/m process model we estimate that RAT power is reduced by 24%.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126944478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Effectiveness and scaling trends of leakage control techniques for sub-130 nm CMOS technologies 130nm以下CMOS技术泄漏控制技术的有效性和缩放趋势
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 1900-01-01 DOI: 10.1109/LPE.2003.1231847
B. Chatterjee, M. Sachdev, S. Hsu, R. Krishnamurthy, S. Borkar
{"title":"Effectiveness and scaling trends of leakage control techniques for sub-130 nm CMOS technologies","authors":"B. Chatterjee, M. Sachdev, S. Hsu, R. Krishnamurthy, S. Borkar","doi":"10.1109/LPE.2003.1231847","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231847","url":null,"abstract":"This paper compares the effectiveness of different leakage control techniques in deep submicron (DSM) bulk CMOS technologies. Simulations show that the 3-5/spl times/ increase in I/sub OFF///spl mu/m per generation is offsetting the savings in switching energy obtained from technology scaling. We compare both the transistor I/sub OFF/ reduction and I/sub ON/ degradation due to each technique for the 130 nm-70 nm technologies. Our results indicate that the effectiveness of leakage control techniques and the associated energy vs. delay tradeoffs depend on the ratio of switching to leakage energies for a given technology. We use our findings to design a 70 nm low power word line driver scheme for a 256 entry, 64-bit register file (R-F). As a result, the leakage (total) energy of the word line drivers is reduced by 3/spl times/ (2.5/spl times/) and for the RF by up to 35% (25%) respectively.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127481709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
B#: a battery emulator and power profiling instrument 一个电池模拟器和功率分析仪器
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 1900-01-01 DOI: 10.1109/LPE.2003.1231879
P. Chou, Chulsung Park, Jae Park, Kien Pham, Jinfeng Liu
{"title":"B#: a battery emulator and power profiling instrument","authors":"P. Chou, Chulsung Park, Jae Park, Kien Pham, Jinfeng Liu","doi":"10.1109/LPE.2003.1231879","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231879","url":null,"abstract":"This paper describes B# (B-sharp), a programmable power supply that emulates the behavior of a battery. It measures the current load, calls a battery simulation program to compute the voltage in real time, and controls a linear regulator to mimic the voltage output of a battery. This instrument enables validation of battery-aware power-optimization techniques with accurate, controllable, reproducible results. This instrument also supports training mode with actual batteries, and it can even be used for recording and playback of a solar power source. This design has been prototyped and tested on hand-held devices with high accuracy and fast response time.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132193975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1-V 1-mW high-speed class AB operational amplifier for high-speed low power pipelined A/D converters using 'Slew boost' technique 1-V - 1-mW高速AB类运算放大器，用于高速低功率流水线A/D转换器，采用“压升压”技术
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 1900-01-01 DOI: 10.1109/LPE.2003.1231891
H. A. Aslanzadeh, S. Mehrmanesh, M. B. Vahidfar, A. Safarian, R. Lotfi
{"title":"A 1-V 1-mW high-speed class AB operational amplifier for high-speed low power pipelined A/D converters using 'Slew boost' technique","authors":"H. A. Aslanzadeh, S. Mehrmanesh, M. B. Vahidfar, A. Safarian, R. Lotfi","doi":"10.1109/LPE.2003.1231891","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231891","url":null,"abstract":"An ultra-low-voltage low-power high-speed class-AB operational amplifier with a new structure is presented. A new technique called 'Slew Boost' is introduced to improve amplifier's large-signal settling behavior, most useful in switched-capacitor circuits such as pipelined ADCs, sigma delta modulators, etc. The proposed op-amp has been designed to be employed in the first stage of a 10 bit 150 MSamples/sec pipelined analog-to-digital converter. Simulation results of the proposed fully-differential class-AB op-amp, using 0.18 /spl mu/m CMOS process models, confirm that it has an output swing of 1.5 Vp-p and consumes less than I mW from a single supply of I volt.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117024461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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