Effectiveness and scaling trends of leakage control techniques for sub-130 nm CMOS technologies

Abstract

This paper compares the effectiveness of different leakage control techniques in deep submicron (DSM) bulk CMOS technologies. Simulations show that the 3-5/spl times/ increase in I/sub OFF///spl mu/m per generation is offsetting the savings in switching energy obtained from technology scaling. We compare both the transistor I/sub OFF/ reduction and I/sub ON/ degradation due to each technique for the 130 nm-70 nm technologies. Our results indicate that the effectiveness of leakage control techniques and the associated energy vs. delay tradeoffs depend on the ratio of switching to leakage energies for a given technology. We use our findings to design a 70 nm low power word line driver scheme for a 256 entry, 64-bit register file (R-F). As a result, the leakage (total) energy of the word line drivers is reduced by 3/spl times/ (2.5/spl times/) and for the RF by up to 35% (25%) respectively.