Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.最新文献_第4页

Analysis of discharge techniques for multiple battery systems 多电池系统放电技术分析

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1109/LPE.2003.1231833

Ravishankar Rao, S. Vrudhula, Daler N. Rakhmatov

{"title":"Analysis of discharge techniques for multiple battery systems","authors":"Ravishankar Rao, S. Vrudhula, Daler N. Rakhmatov","doi":"10.1109/LPE.2003.1231833","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231833","url":null,"abstract":"We consider the problem of scheduling multiple identical batteries for discharge in portable electronic systems. Unlike previous work reporting some experimental data to suggest which scheduling schemes are better than others, we arrive at our general conclusions formally, based on the analysis of an accurate high-level model of battery behavior. Our analytical results show that: (1) the lifetime of a parallel discharge schedule is equal to that of an equivalent monolithic battery, (2) the lifetime of a parallel discharge-schedule is no less than that of a sequential discharge schedule, and (3) the lifetime of a switched discharge schedule approaches that of an equivalent monolithic battery as the switching frequency increases. We also derive bounds on the lifetime of a single battery under a constant-rate load, and then extend them to multiple battery systems. Using a low-level battery simulator, we verify our analytical findings with numerical data. For the simulated cases, the parallel discharge schedule resulted in up to 72% higher lifetimes than the sequential discharge schedule but fell short of the lifetime tipper bound by up to 29%.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114372252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 29

Pipeline stage unification: a low-energy consumption technique for future mobile processors 流水线阶段统一:未来移动处理器的低能耗技术

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1145/871506.871587

Hajime Shimada, H. Ando, T. Shimada

引用次数: 48

Energy-aware memory allocation in heterogeneous non-volatile memory systems 异构非易失性存储系统中的能量感知内存分配

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1145/871506.871609

H. Lee, N. Chang

引用次数: 42

Efficient techniques for gate leakage estimation 栅极泄漏估计的有效技术

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1145/871506.871533

R. Rao, J. Burns, A. Devgan, Richard B. Brown

引用次数: 83

The microarchitecture of a low power register file 低功耗寄存器文件的微结构

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1109/LPE.2003.1231931

N. Kim, T. Mudge

{"title":"The microarchitecture of a low power register file","authors":"N. Kim, T. Mudge","doi":"10.1109/LPE.2003.1231931","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231931","url":null,"abstract":"The access time, energy and area of the register file are often critical to overall performance in wide-issue microprocessors, because these terms grow superlinearly with the number of read and write ports that are required to support wide-issue. This paper presents two techniques to reduce the number of ports of a register file intended for a wide-issue microprocessor with hardly any impact on IPC. Our results show that it is possible to replace a register file with 16 read and 8 write ports, intended for an eight-issue processor, with a register file with just 8 read and 8 write ports so that the impact on IPC is a few percent. This is accomplished with the addition of several small auxiliary memory structures, a 'delayed write-back queue' and an 'operand prefetch buffer.' We examine several configurations employing these structures separately and in combination. In the case of just the delayed write-back queue, we show an energy per access savings of about 40% and an area savings of 40% . This incurs a performance loss of just 4%. The area savings in turn has the potential for further savings by shortening global interconnect in the layout. We also show that the performance loss can be almost eliminated if both techniques are used in combination, although some area and power savings is lost.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116790503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30

A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime 一种耐噪高速缓存设计，可减少纳米级栅极和亚阈值泄漏

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1145/871506.871514

A. Agarwal, K. Roy

{"title":"A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime","authors":"A. Agarwal, K. Roy","doi":"10.1145/871506.871514","DOIUrl":"https://doi.org/10.1145/871506.871514","url":null,"abstract":"Scaling devices while maintaining reasonable short channel immunity requires gate oxide thickness of less than 20 /spl Aring/ for CMOS devices beyond the 70 nm technology node. Low oxide thickness gives rise to considerable direct tunneling current (gate leakage). Power dissipation in large caches is dominated by the gate and sub-threshold leakage current. This paper proposes a novel cache that has high noise immunity with improved leakage power. For every bank of SRAM cells, this technique requires an extra diode in parallel with a gated-ground transistor connected between the source of NMOS transistors and ground in SRAM cells. The row decoder itself can be used to control the extra gated-ground transistor. Our simulation results on a 70 nm process (Berkeley Predictive Technology Model augmented with our gate leakage model) show 39.2% reduction in consumed energy (leakage plus dynamic) in L1 cache and 59.4% reduction in L2 cache energy with less than 2.5% impact on execution time. The technique is applicable to data and instruction caches as well as different levels of cache hierarchy such as the L1, L2, or L3 caches.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131423761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 43

Integrated DC-DC converter design for improved WCDMA power amplifier efficiency in SiGe BiCMOS technology 集成DC-DC变换器设计，提高了SiGe BiCMOS技术中WCDMA功率放大器的效率

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1145/871506.871617

D. Guckenberger, K. Kornegay

引用次数: 20

Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation 基于 MOS 的温度和工艺不变基准电流发生电路，可实现 1V 以下电压运行

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1109/LPE.2003.1231862

Stephen Tang, S. Narendra, V. De

引用次数: 22

Leakage and leakage sensitivity computation for combinational circuits 组合电路的泄漏和泄漏灵敏度计算

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1145/871506.871532

E. Acar, A. Devgan, R. Rao, Y. Liu, Haihua Su, S. Nassif, J. Burns

引用次数: 35

Energy recovery clocking scheme and flip-flops for ultra low-energy applications 超低能耗应用的能量恢复时钟方案和触发器

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI: 10.1109/LPE.2003.1231835

M. Cooke, H. Mahmoodi, K. Roy

{"title":"Energy recovery clocking scheme and flip-flops for ultra low-energy applications","authors":"M. Cooke, H. Mahmoodi, K. Roy","doi":"10.1109/LPE.2003.1231835","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231835","url":null,"abstract":"A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes would be promising approaches for future designs. We propose four novel energy recovery flip-flops that enable energy recovery from the clock network, resulting in significant energy savings. The proposed flip-flops operate with a single-phase sinusoidal clock, which can be generated with high efficiency. Based on the simulation results using TSMC 0.25 /spl mu/m CMOS process technology, at a frequency of 200 MHz, the proposed flip-flops exhibit more than 80% delay reduction, power reduction of up to 46%, and area reduction of up to 77%, as compared to the conventional energy recovery flip-flop. We implemented 1024 proposed energy recovery flip-flops through an H-tree clock network driven by a resonant clock-generator that generates a sinusoidal clock. Results show a power reduction of 90% on the clock-tree and total power savings of up to 83% as compared to the same implementation using the conventional square-wave clocking scheme and flip-flops.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115483904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 40