2011 IEEE 29th International Conference on Computer Design (ICCD)最新文献_第3页

TAP prediction: Reusing conditional branch predictor for indirect branches with Target Address Pointers TAP预测:为带有目标地址指针的间接分支重用条件分支预测器

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081386

Zichao Xie, Dong Tong, Mingkai Huang, Xiaoyin Wang, Qinqing Shi, Xu Cheng

{"title":"TAP prediction: Reusing conditional branch predictor for indirect branches with Target Address Pointers","authors":"Zichao Xie, Dong Tong, Mingkai Huang, Xiaoyin Wang, Qinqing Shi, Xu Cheng","doi":"10.1109/ICCD.2011.6081386","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081386","url":null,"abstract":"Indirect-branch prediction is becoming more important for modern processors as more programs are written in object-oriented languages. Previous hardware-based indirect-branch predictors generally require significant hardware storage or use aggressive algorithms which make the processor front-end more complex. In this paper, we propose a fast and cost-efficient indirect-branch prediction strategy, called Target Address Pointer (TAP) Prediction. TAP Prediction reuses the history-based branch direction predictor to detect occurrences of indirect branches, and then stores indirect-branch targets in the Branch Target Buffer (BTB). The key idea of TAP Prediction is to predict the Target Address Pointers, which generate virtual addresses to index the targets stored in the BTB, rather than to predict the indirect-branch targets directly. TAP Prediction also reuses the branch direction predictor to construct several small predictors. When fetching an indirect branch, these small predictors work in parallel to generate the target address pointer. Then TAP prediction accesses the BTB to fetch the predicted indirect-branch target using the generated virtual address. This mechanism could achieve time cost comparable to that of dedicated-storage-predictors, without requiring additional large amounts of storage. Our evaluation shows that for three representative direction predictors-Hybrid, Perceptrons, and O-GEHL-TAP schemes improve performance by 18.19%, 21.52%, and 20.59%, respectively, over the baseline processor with the most commonly-used BTB prediction. Compared with previous hardware-based indirect-branch predictors, the TAP-Perceptrons scheme achieves performance improvement equivalent to that provided by a 48KB TTC predictor, and it also outperforms the VPC predictor by 14.02%.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133017877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Improving GPU Robustness by making use of faulty parts 利用故障部件提高GPU鲁棒性

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081422

Artem Durytskyy, M. Zahran, R. Karri

引用次数: 8

Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores 设计三维内嵌岩芯粘接前、粘接后的三维测试封装器

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081381

D. L. Lewis, Shreepad Panth, Xin Zhao, S. Lim, H. Lee

引用次数: 19

Fast and compact binary-to-BCD conversion circuits for decimal multiplication 用于十进制乘法的快速和紧凑的二进制到bcd转换电路

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081401

O. Al-Khaleel, Zakaria Al-Qudah, M. Al-khaleel, C. Papachristou, F. Wolff

{"title":"Fast and compact binary-to-BCD conversion circuits for decimal multiplication","authors":"O. Al-Khaleel, Zakaria Al-Qudah, M. Al-khaleel, C. Papachristou, F. Wolff","doi":"10.1109/ICCD.2011.6081401","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081401","url":null,"abstract":"Decimal arithmetic has received considerable attention recently due to its suitability for many financial and commercial applications. In particular, numerous algorithms have been recently proposed for decimal multiplication. A major approach to decimal multiplication shaped by these proposals is based on performing the decimal digit-by-digit multiplication in binary, converting the binary partial product back to decimal, and then adding the decimal partial products as appropriate to form the final product in decimal. With this approach, the efficiency of binary-to-BCD partial product conversion is critical for the efficiency of the overall multiplication process. A recently proposed algorithm for this conversion is based on splitting the binary partial product into two parts (i.e., two groups of bits), and then computing the contributions of the two parts to the partial BCD result in parallel. This paper proposes two new algorithms (Three-Four split and Four-Three split) based on this principle. We present our proposed architectures that implement these algorithms and compare them to existing algorithms. The synthesis results show that the Three-Four split algorithm runs 15%faster and occupies 26.1%less area than the best performing equivalent circuit found in the literature. Furthermore, the Four-Three split algorithm occupies 37.5% less area than the state of the art equivalent circuit.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128577438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

Energy aware task mapping algorithm for heterogeneous MPSoC based architectures 基于异构MPSoC架构的能量感知任务映射算法

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081444

A. Hussien, A. Eltawil, R. Amin, Jim Martin

引用次数: 9

A memristor-based memory cell using ambipolar operation 使用双极性操作的基于记忆器的存储单元

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081390

P. Junsangsri, F. Lombardi

引用次数: 15

Blue team red team approach to hardware trust assessment 蓝队红队硬件信任评估方法

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081410

Jeyavijayan Rajendran, V. Jyothi, R. Karri

引用次数: 33

Enhanced symbolic simulation of a round-robin arbiter 轮询仲裁器的增强符号模拟

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081383

Yongjian Li, Naiju Zeng, W. Hung, Xiaoyu Song

引用次数: 5

Simultaneous continual flow pipeline architecture 同时连续流管道结构

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081387

K. Jothi, Mageda Sharafeddine, Haitham Akkary

引用次数: 8

Using content-aware bitcells to reduce static energy dissipation 使用内容感知位元来减少静态能量耗散

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081375

Fahrettin Koc, O. Simsek, O. Ergin

引用次数: 5