2011 IEEE 29th International Conference on Computer Design (ICCD)最新文献

EM and circuit co-simulation of a reconfigurable hybrid wireless NoC on 2D ICs 二维集成电路上可重构混合无线NoC的电磁与电路联合仿真

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081370

A. More, B. Taskin

引用次数: 5

Analysis of reliability of flip-flops under transistor aging effects in nano-scale CMOS technology 纳米级CMOS技术中晶体管老化效应下触发器可靠性分析

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081439

V. G. Rao, H. Mahmoodi

引用次数: 27

A morphable phase change memory architecture considering frequent zero values 一种考虑频繁零值的可变形相变存储器结构

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081426

M. Arjomand, A. Jadidi, Ali Shafiee, H. Sarbazi-Azad

{"title":"A morphable phase change memory architecture considering frequent zero values","authors":"M. Arjomand, A. Jadidi, Ali Shafiee, H. Sarbazi-Azad","doi":"10.1109/ICCD.2011.6081426","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081426","url":null,"abstract":"Phase Change Memory (PCM) is emerging as a high-dense and power-efficient choice for future main memory systems. While PCM cell size is marching towards minimum achievable feature size, recent prototypes effectively improve device scalability by storing multiple bits per each cell. Unfortunately, Multi-Level Cell (MLC) PCM devices offer higher access time and energy when compared to Single-Level Cell (SLC) counterparts making it difficult to incorporate MLC in main memory. To address this challenge, we proposes Zero-value-based Morphable PCM, ZM-PCM for short, a novel MLC-PCM main memory architecture which tries incorporating benefits of both MLC and SLC devices within the same structure. ZM-PCM relies on the observation that zero value at various granularities is frequently occurred within main memory transactions when running PARSEC-2 programs. Motivated by this observation, ZM-PCM codes redundant zero MLC cells into limited bits that is storable in the SLC (or alternatively in devices with fewer bits) form with improved latency, energy, and lifetime with no reduction in available main memory capacity. We evaluate microarchitecture design of morphable PCM cell, coding and decoding algorithms and details of related circuits. We also introduce a simple area-efficient caching mechanism for fast cost-efficient access to coding metadata. Our evaluation on a quad-core CMP with 4GB 8-bit MLC PCM main memory shows that ZM-PCM morphs up to 93% (and 50% on average) of all memory cells with lower densities which directly turns in performance, power and lifetime enhancement.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127114068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 23

Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors 具有延迟和泄漏的基于3t1d监视器的缓存的动态细粒度体偏置

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081420

Shrikanth Ganapathy, R. Canal, Antonio González, A. Rubio

{"title":"Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors","authors":"Shrikanth Ganapathy, R. Canal, Antonio González, A. Rubio","doi":"10.1109/ICCD.2011.6081420","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081420","url":null,"abstract":"In this paper, we propose a dynamically tunable fine-grain body biasing mechanism to reduce standby leakage power in first level data-caches under process variations. Accessed physical arrays are forward body biased (FBB) to improve latency while idle (unaccessed) arrays are reverse body biased (RBB) for reducing standby leakage power. The bias voltage to be applied is computed at design time and updated at run-time to counter the negative effects of process variations. This ensures that under all scenarios, the cache will consume the lowest leakage power for the target access latency computed at design-time. A sensor-like hardware mechanism measures the variation in latency and leakage at run-time and this measurement is used to update the bias voltage. The backbone of the hardware used for measurement is a three-transistor one-diode(3T1D)DRAM cell embedded into a regular cache array. By measuring the access and retention time of the 3T1D cell, we show that it is possible to classify cache arrays based on run-time latency/leakage profiles. Our technique reduces leakage energy consumption and access latency of the cache on an average by 20% & 18% respectively. Finally we show that our technique will improve parametric yield by a maximum of 38% for worst-case scenario.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127890568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Static window addition: A new paradigm for the design of variable latency adders 静态窗口添加:一种设计可变延迟加法器的新范例

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081446

Kai Du, P. Varman, K. Mohanram

引用次数: 4

Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors 多路容错芯片多处理器的自适应执行辅助

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081432

Pramod Subramanyan, Virendra Singh, K. Saluja, E. Larsson

引用次数: 1

FIMSIM: A fault injection infrastructure for microarchitectural simulators 用于微架构模拟器的故障注入基础设施

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081435

Gulay Yalcin, O. Unsal, A. Cristal, M. Valero

引用次数: 26

A novel software-based defect-tolerance approach for application-specific embedded systems 针对特定应用的嵌入式系统的一种新的基于软件的容错方法

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081441

Da Cheng, S. Gupta

引用次数: 7

Adaptable architectures for distributed visual target tracking 分布式视觉目标跟踪的适应性体系结构

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081421

Domenic Forte, Ankur Srivastava

引用次数: 3

A machine learning approach to modeling power and performance of chip multiprocessors 用机器学习方法对芯片多处理器的功率和性能进行建模

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081374

Changshu Zhang, A. Ravindran, Kushal Datta, A. Mukherjee, B. Joshi

引用次数: 4