2011 IEEE 29th International Conference on Computer Design (ICCD)最新文献_第2页

An optimized scaled neural branch predictor 一个优化的神经分支预测器

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081385

Daniel A. Jiménez

引用次数: 27

Tree structured analysis on GPU power study GPU功耗研究的树结构分析

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081376

Jianmin Chen, Bin Li, Ying Zhang, Lu Peng, J. Peir

{"title":"Tree structured analysis on GPU power study","authors":"Jianmin Chen, Bin Li, Ying Zhang, Lu Peng, J. Peir","doi":"10.1109/ICCD.2011.6081376","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081376","url":null,"abstract":"Graphics Processing Units (GPUs) have emerged as a promising platform for parallel computation. With a large number of processor cores and abundant memory bandwidth, GPUs deliver substantial computation power. While providing high computation performance, a GPU consumes high power and needs sufficient power supplies and cooling systems. It is essential to institute an efficient mechanism for evaluating and understanding the power consumption when running real applications on high-end GPUs. In this paper, we present a high-level GPU power consumption model using sophisticated tree-based random forest methods which correlate and predict the power consumption using a set of performance variables. We demonstrate that this statistical model not only predicts the GPU runtime power consumption more accurately than existing regression based approaches, but more importantly, it provides sufficient insights into understanding the correlation of the GPU power consumption with individual performance metrics. We use a GPU simulator that can collect more runtime performance metrics than hardware counters. We measure the power consumption of a wide-range of CUDA kernels on an experimental system with GTX 280 GPU to collect statistical samples for power analysis. The proposed method is applicable to other GPUs as well.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128944953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 28

A study on relating redundancy removal in classical circuits to reversible mapping 经典电路冗余去除与可逆映射的关系研究

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081398

S. Sultana, K. Radecka, Yu Pang

引用次数: 2

ROA-brick topology for rotary resonant clocks 旋转谐振时钟的roa砖拓扑结构

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081408

Y. Teng, Jianchao Lu, B. Taskin

引用次数: 8

Reduced complexity test generation algorithms for transition fault diagnosis 转换故障诊断的低复杂度测试生成算法

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081382

Yu Zhang, V. Agrawal

引用次数: 20

Precise exception support for decoupled run-time monitoring architectures 对解耦运行时监视体系结构的精确异常支持

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081438

Daniel Y. Deng, G. Suh

引用次数: 1

A novel shared-buffer router for network-on-chip based on Hierarchical Bit-line Buffer 一种基于分层位线缓冲器的片上网络共享缓冲路由器

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081407

Wei Shi, Weixia Xu, Hongguang Ren, Q. Dou, Zhiying Wang, Li Shen, Cong Liu

{"title":"A novel shared-buffer router for network-on-chip based on Hierarchical Bit-line Buffer","authors":"Wei Shi, Weixia Xu, Hongguang Ren, Q. Dou, Zhiying Wang, Li Shen, Cong Liu","doi":"10.1109/ICCD.2011.6081407","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081407","url":null,"abstract":"Buffer resources are key components of the on-chip router, shared-buffer structures are proposed to improve performance and reduce power consumption. This paper presents a novel on-chip network router with a shared-buffer based on Hierarchical Bit-line Buffer (HiBB). HiBB can be configured flexibly according to traffics and its inherent characteristic of low power is also noticeable. Moreover, we propose two schemes to further optimize the router. First, a congestion-aware output-port allocation scheme is used to assign higher priority to packets heading to light-loaded directions, and the congestion situation of the total network will be addressed. Second, an efficient run-time Virtual Channel (VC) regulation scheme is proposed to configure the shared buffer, so that VCs are allocated according to the loads of network. Experimental results show that the proposed HiBB router with about 6.9% area savings outperforms the generic router under different traffic patterns. The power consumption of the HiBB router can also be reduced up to about 70% of the generic router under light traffics, while it may exceed that of the generic one up to about 3.7–5.7% under heavy traffics for the increased flit transmissions.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121632552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Applying verification intention for design customization via property mining under constrained testbenches 通过约束测试台架下的属性挖掘，将验证意图应用于设计定制

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081380

Chih-Neng Chung, Chia-Wei Chang, Kai-Hui Chang, S. Kuo

引用次数: 5

CPACT - The conditional parameter adjustment cache tuner for dual-core architectures CPACT——用于双核架构的条件参数调整缓存调谐器

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081429

M. Rawlins, A. Gordon-Ross

引用次数: 12

Task model for on-chip communication infrastructure design for multicore systems 多核系统片上通信基础设施设计的任务模型

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081424

Bharath Phanibhushana, Kunal P. Ganeshpure, S. Kundu

{"title":"Task model for on-chip communication infrastructure design for multicore systems","authors":"Bharath Phanibhushana, Kunal P. Ganeshpure, S. Kundu","doi":"10.1109/ICCD.2011.6081424","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081424","url":null,"abstract":"With technology scaling, Multiprocessor System on Chip (MPSoC) which consist of multiple processors connected via a Network on Chip (NoC) have become prevalent. Applications are mapped to MPSoC's by representing it in the form of a task graph. Task scheduling involves mapping task to processor cores so as to meet the deadline. For a given deadline, slack at each node is defined by the amount of time by which a task execution can be delayed without missing the deadline. With increase in the number of cores and high application parallelism, NoC is becoming a bottleneck due to the presence of large number of concurrent communications. Increasing network resources (links and routers) reduces the communication time but the area and power goes up. In this paper we present an application aware heuristic to synthesize a minimal network connecting a set of cores in an MPSoC in the presence of hard deadlines. Our approach is based on modeling communication between a pair of processors as tasks known as “Comtasks”. The network is generated by “scheduling” these comtasks onto a set of routers so as to obtain a network with minimum area which fills up the available slack. Moreover, we also identify the set of overlapping comtasks and generate a minimal network to allow the maximum set of overlapping comtasks to execute concurrently. We compared our approach with a greedy network generation heuristic and the results show 80% benefit in the router area.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134009757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11