Applying verification intention for design customization via property mining under constrained testbenches

Abstract

Most synthesis tools perform optimizations based on the design itself and do not utilize the information present in the verification environment. Not using such information greatly limits the optimization capabilities of synthesis tools, which is especially serious for circuit customization because most environment constraints are encoded in the testbench. To exploit verification intention, we propose a methodology that utilizes functional assertions for design optimization. To support circuit customization, we also propose a property mining technique that can extract properties from the design under the constraints in the testbench. Our experimental results show that these methods can reduce design size after synthesis, and the optimization is orthogonal to other existing circuit customization methods.