2011 IEEE 29th International Conference on Computer Design (ICCD)最新文献_第4页

Memristor-based IMPLY logic design procedure 基于记忆电阻的隐式逻辑设计程序

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081389

Shahar Kvatinsky, A. Kolodny, U. Weiser, E. Friedman

引用次数: 147

RoShaQ: High-performance on-chip router with shared queues RoShaQ:具有共享队列的高性能片上路由器

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081402

A. Tran, B. Baas

{"title":"RoShaQ: High-performance on-chip router with shared queues","authors":"A. Tran, B. Baas","doi":"10.1109/ICCD.2011.6081402","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081402","url":null,"abstract":"On-chip router typically has buffers dedicated to its input or output ports for temporarily storing packets in case contention occurs on output physical channels. Buffers, unfortunately, consume significant portions of router area and power. While running a traffic trace, however, not all input ports of routers have incoming packets needed to be transferred at the same time. As a result, a large number of buffer queues in the network are empty while other queues are mostly busy. This observation motivates us to design RoShaQ, a router architecture that maximizes buffer utilization by allowing to share multiple buffer queues among input ports. Sharing queues, in fact, makes using buffers more efficient hence is able to achieve higher throughput when the network load becomes heavy. On the other side, at light traffic load, our router achieves low latency by allowing packets to effectively bypass these shared queues. Experimental results show that RoShaQ is 21% less latency and 14% higher saturation throughput than a typical virtual-channel (VC) router with 4% higher power and 16% larger area. Due to its higher performance, RoShaQ consumes 7% less energy per a transferred packet than a VC router given the same buffer space capacity.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127076483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 49

A simple pipelined squaring circuit for DSP 一个简单的流水线平方电路的DSP

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081392

V. Risojevic, A. Avramović, Z. Babic, P. Bulić

引用次数: 9

Hardware Trojans: The defense and attack of integrated circuits 硬件木马:集成电路的防御和攻击

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081412

Trey Reece, W. H. Robinson

引用次数: 9

The DIMM tree architecture: A high bandwidth and scalable memory system 内存树结构:高带宽和可扩展的内存系统

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081428

Kanit Therdsteerasukdi, Gyungsu Byun, J. Ir, Glenn D. Reinman, J. Cong, Mau-Chung Frank Chang

引用次数: 22

A reconfigurable fault-tolerant routing algorithm to optimize the network-on-chip performance and latency in presence of intermittent and permanent faults 一种可重构的容错路由算法，用于优化片上网络在间歇性和永久性故障下的性能和延迟

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081436

Reyhaneh Jabbarvand Behrouz, M. Modarressi, H. Sarbazi-Azad

引用次数: 3

Red team: Design of intelligent hardware trojans with known defense schemes 红队:设计具有已知防御方案的智能硬件木马

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081416

Xuehui Zhang, Nicholas Tuzzio, M. Tehranipoor

引用次数: 12

Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory 探讨三维堆叠非易失性存储器的cmp软错误脆弱性

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1145/2491679

Guangyu Sun, E. Kursun, J. Rivers, Yuan Xie

引用次数: 24

Techniques for LI-BDN synthesis for hybrid microarchitectural simulation 混合微建筑模拟中LI-BDN合成技术

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081405

Tyler S. Harris, Zhuo Ruan, D. Penry

{"title":"Techniques for LI-BDN synthesis for hybrid microarchitectural simulation","authors":"Tyler S. Harris, Zhuo Ruan, D. Penry","doi":"10.1109/ICCD.2011.6081405","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081405","url":null,"abstract":"Computer designers rely upon near-cycle-accurate microarchitectural simulation to explore the design space of new systems. Unfortunately, such simulators are becoming increasingly slow as systems become more complex. Hybrid simulators which offload some of the simulation work onto FPGAs can increase the speed; however, such simulators must be automatically synthesized or the time to design them becomes prohibitive. Furthermore, FPGA implementations of simulators may require multiple FPGA clock cycles to implement behavior that takes place within one simulated clock cycle, making correct arbitrary composition of simulator components impossible and limiting the amount of hardware concurrency which can be achieved. Latency-Insensitive Bounded Dataflow Networks (LI-BDNs) have been suggested as a means to permit composition of simulator components in FPGAs. However, previous work has required that LI-BDNs be created manually. This paper introduces techniques for automated synthesis of LI-BDNs from the processes of a System-C microarchitectural model. We demonstrate that LI-BDNs can be successfully synthesized. We also introduce a technique for reducing the overhead of LI-BDNs when the latency-insensitive property is unnecessary, resulting in up to a 60% reduction in FPGA resource requirements.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"282 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120963477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Positive Davio-based synthesis algorithm for reversible logic 基于正david的可逆逻辑综合算法

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081399

Yu Pang, Shaoquan Wang, Zhilong He, Jinzhao Lin, S. Sultana, K. Radecka

引用次数: 21