2011 IEEE 29th International Conference on Computer Design (ICCD)最新文献_第5页

Energy-aware Standby-Sparing Technique for periodic real-time applications 周期性实时应用的能量感知备用节省技术

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081396

M. A. Haque, Hakan Aydin, Dakai Zhu

引用次数: 53

Output process of variable bit-rate flows in on-chip networks based on aggregate scheduling 基于聚合调度的片上网络可变比特率流输出过程

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081442

Fahimeh Jafari, A. Jantsch, Zhonghai Lu

引用次数: 4

Video quality-driven buffer dimensioning in MPSoC platforms via prioritized frame drops 视频质量驱动的MPSoC平台中通过优先帧丢失的缓冲区尺寸

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081404

Deepak Gangadharan, Haiyang Ma, S. Chakraborty, Roger Zimmermann

引用次数: 2

3D vs. 2D analysis of FinFET logic gates under process variations 工艺变化下FinFET逻辑门的3D与2D分析

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081437

S. Chaudhuri, N. Jha

{"title":"3D vs. 2D analysis of FinFET logic gates under process variations","authors":"S. Chaudhuri, N. Jha","doi":"10.1109/ICCD.2011.6081437","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081437","url":null,"abstract":"Among various multi-gate structures, FinFETs have emerged dominant owing to their ease of fabrication. Thus, characterization of FinFET devices/gates needs immediate attention for them to become the industry driver in this decade. Ideally, 3D device simulation should be done to enable accurate circuit synthesis. However, this is impractical due to the huge CPU times required. Simulating a 2D cross-section of the device yields 100–1000× reduction in CPU time. However, this introduces significant error, in the range of 10% to 50%, while evaluating the on/off current (ION/IOFF) for a single device and leakage current or propagation delay (ILEAK/tD) for logic gates. In this work, we develop accurate 2D models of FinFET devices to capture 3D simulation accuracy with 2D simulation efficiency. We report results for the 22nm FinFET technology node. As far as we know, this is the first such attempt. We establish the validity of the model even under process variations. We target variations in gate length (LG), workfunction (ΦG) and fin thickness (TSI) that are known to have the most impact on leakage and delay. We adjust their values in the 2D model in order to mimic the actual 3D device behavior. When the 2D models are employed in mixed-mode simulation of FinFET logic gates, the error in the evaluation of ILEAK/tD is quite small.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"298 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134265279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

Using analog circuit behavior to generate SystemC events for an acceleration of mixed-signal simulation 使用模拟电路行为来生成SystemC事件，以加速混合信号仿真

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081384

Stefan Hoelldampf, D. Zaum, M. Olbrich, E. Barke

引用次数: 8

Leveraging torus topology with deadlock recovery for cost-efficient on-chip network 利用环面拓扑与死锁恢复为成本效益的片上网络

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081371

Minjeong Shin, John Kim

{"title":"Leveraging torus topology with deadlock recovery for cost-efficient on-chip network","authors":"Minjeong Shin, John Kim","doi":"10.1109/ICCD.2011.6081371","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081371","url":null,"abstract":"On-chip networks are becoming more important as the number of on-chip components continue to increase. 2D mesh topology is a commonly assumed topology for on-chip networks but in this work, we make the argument that 2D torus can provide a more cost-efficient on-chip network since the on-chip network datapath is reduced by 2× while providing the same bisection bandwidth as a mesh network. Our results show that 2D torus can achieve an improvement of up to 1.9× over a 2D mesh in performance per watt metric. However, routing deadlock can occur in a torus network with the wrap-around channel and requires additional virtual channels for deadlock avoidance. In this work, we propose deadlock recovery with tokens (DRT) in on-chip networks that exploits on-chip networks - exploiting the abundant wires available while minimizing the need for additional buffers. As a result, deadlocks can be exactly detected without having to rely on a timeout mechanism and when needed, recover from the deadlock. We show how DRT results in minimal loss in performance, compared with deadlock avoidance using virtual channels, while reducing the on-chip network complexity.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"238 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116176321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

A novel cryptographic key exchange scheme using resistors 一种利用电阻器的新型密码密钥交换方案

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081445

P. Lin, A. Ivanov, Bradley Johnson, S. Khatri

引用次数: 3

Using stochastic computing to implement digital image processing algorithms 利用随机计算实现数字图像处理算法

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081391

Peng Li, D. Lilja

{"title":"Using stochastic computing to implement digital image processing algorithms","authors":"Peng Li, D. Lilja","doi":"10.1109/ICCD.2011.6081391","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081391","url":null,"abstract":"As device scaling continues to nanoscale dimensions, circuit reliability will continue to become an ever greater problem. Stochastic computing, which performs computing with random bits (stochastic bits streams), can be used to enable reliable computation using those unreliable devices. However, one of the major issues of stochastic computing is that applications implemented with this technique are limited by the available computational elements. In this paper, first we will introduce and prove a stochastic absolute value function. Second, we will demonstrate a mathematical analysis of a stochastic tanh function, which is a key component used in a stochastic comparator. Third, we will present a quantitative analysis of a one-parameter linear gain function, and propose a new two-parameter version. The validity of the present stochastic computational elements is demonstrated through four basic digital image processing algorithms: edge detection, frame difference based image segmentation, median filter based noise reduction, and image contrast stretching. Our experimental results show that stochastic implementations tolerate more noise and consume less hardware than their conventional counterparts.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114754071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 145

Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset 多节点扰动下单事件硬化纳米级存储单元建模与设计

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081418

Sheng Lin, Yong-Bin Kim, F. Lombardi

{"title":"Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset","authors":"Sheng Lin, Yong-Bin Kim, F. Lombardi","doi":"10.1109/ICCD.2011.6081418","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081418","url":null,"abstract":"The occurrence of a multiple node upset is likely to increase significantly in nanoscale CMOS due to reduced device size and power supply voltage scaling. This paper presents a comprehensive treatment (model, analysis and design) for hardening a memory cell against a soft error resulting in a multiple node upset at 32nm feature size in CMOS. A novel 13T memory cell configuration is proposed, analyzed, and simulated to show a better tolerance to the likely multiple node upset, i.e. a transient or soft fault affecting any two nodes in a cell. The proposed hardened memory cell utilizes a Schmitt trigger design; simulation shows that the multiple node upset tolerance is improved by nearly twice as much over existing designs. Moreover the 13T cell achieves a 33% reduction in write delay and only a 5% increase in power consumption compared to the DICE cell (consisting of 12 transistors). Simulation results are provided using the predictive technology file for 32nm feature size in CMOS. Monte Carlo simulation confirms the excellent multiple node upset tolerance of the proposed memory cell in the presence of process, voltage, and temperature variations in their designs.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114425806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Analysis of on-chip interconnection network interface reliability in multicore systems 多核系统片上互连网络接口可靠性分析

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI: 10.1109/ICCD.2011.6081433

Yong Zou, Yi Xiang, S. Pasricha

引用次数: 2