Using content-aware bitcells to reduce static energy dissipation

Abstract

Static energy dissipation is an increasing problem in contemporary processor design with shrinking feature sizes. Many schemes are proposed to cope with leakage in the literature ranging from using sleep transistors to lowering supply voltage. In this paper, we introduce a Conscious SRAM (CSRAM) design to lower static energy dissipation in the storage components of a processor. The proposed bitcell design adapts the body bias of its own transistors according to its contents. We show that the use of the proposed CSRAM cells results in significant reduction in the static energy dissipation of on-chip storage components without significant performance degradation. In order to reduce the area overhead introduced by the CSRAM we propose a simplified version of the cell at the circuit level. We also leverage the fact that the contents of adjacent bits of the stored values are highly dependent on each other, especially on the upper order bits of a value, and propose some architectural level solutions that lower the area overhead to as low as 7%.