轮询仲裁器的增强符号模拟

2011 IEEE 29th International Conference on Computer Design (ICCD) Pub Date : 2011-10-09 DOI:10.1109/ICCD.2011.6081383

Yongjian Li, Naiju Zeng, W. Hung, Xiaoyu Song

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引用次数: 5

摘要

在这项工作中，我们对轮询仲裁器的硬件设计进行了形式化的验证，轮询仲裁器是许多实际网络系统中的核心组件。我们的方法是增强的STE，它不仅探索了一轮轮询仲裁的完全符号模拟，而且还探索了仲裁器的顺序行为。我们的实验表明，增强的STE规范可以在合理的时间和内存使用情况下自动完成实际硬件设计。

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Enhanced symbolic simulation of a round-robin arbiter

In this work, we present our results on formally verifying hardware design of round-robin arbiter which is the core component in many real network systems. Our approach is enhanced STE, which explores fully symbolic simulation for not only one round of round-robin arbitration, but also the sequential behaviors of the arbiter. Our experiments demonstrate that the enhanced STE specification for real-world hardware design can be finished automatically in a reasonable time and memory usage.

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2011 IEEE 29th International Conference on Computer Design (ICCD)

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