2021 IEEE 71st Electronic Components and Technology Conference (ECTC)最新文献

{"title":"Reliability Modeling of Micro-vias in High-Density Redistribution Layers","authors":"Pratik Nimbalkar, M. Kathaperumal, Fuhan Liu, M. Swaminathan, R. Tummala","doi":"10.1109/ECTC32696.2021.00161","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00161","url":null,"abstract":"The ever-increasing demand for high-bandwidth interconnects has given rise to the need for high IO-density package redistribution layers (RDL). This necessitates scaling down RDL critical dimensions as well as microvias. There are numerous challenges pertaining to scaling down microvias below $5 mu mathrm{m}$ diameter. The main challenge is the thermomechanical reliability of vias in polymer dielectrics. Modeling and design for reliability in various polymer dielectrics is the key to achieve mechanical reliability. This paper presents a model for the prediction of micro-via failure. The effects of via geometry such as-via angle and height as well as material properties such as-CTE and elastic modulus on via failure are presented. Furthermore, modeling results are correlated with experimental results to verify the accuracy of the model. Using this model, it was determined that the conventional via geometry reaches an engineering limit at $2 mu mathrm{m}$ of via diameter. Below this size, it becomes difficult to achieve reliable vias in polymers as they do not survive 1000 thermal cycles. Based on the modeling studies, a novel method is proposed for enhancement of reliability of vias below the engineering limit of $2 mu mathrm{m}$.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125475521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Plasma Activated Low-temperature Die-level Direct Bonding with Advanced Wafer Dicing Technologies for 3D Heterogeneous Integration","authors":"K. Sakuma, Dishit P. Parekh, M. Belyansky, Juan-Manuel Gomez, S. Skordas, D. Mcherron, I. de Sousa, Marc-Antoine K. Phaneuf, Martin M Desrochers, Ming Li, Y. Cheung, Siu Cheung So, S. Kwok, Chun Ho Fan, Siu Wing Lau","doi":"10.1109/ECTC32696.2021.00075","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00075","url":null,"abstract":"In this paper, we have demonstrated a plasma activated low-temperature die-level oxide-oxide direct bonding with advanced wafer dicing technologies. This evaluation used blanket 300-mm silicon wafers. $1 mumathrm{m}$ Tetraethyl orthosilicate (TEOS) oxide was deposited by plasma-enhanced chemical vapor deposition (PECVD) directly on the silicon (Si) wafer surface, followed by chemical mechanical planarization (CMP). Atomic Force Microscopy (AFM) was used to examine the roughness of the wafer surface before dicing and it showed < 0.38 nm RMS and < 0.30 nm $mathrm{R}_{mathrm{a}}$. Several dicing technologies such as diamond blade dicing, step-cut blade dicing, bevel blade dicing, and stealth laser dicing were evaluated for this integration scheme. In the end, diamond blade dicing has the most compatibility with many materials, but it led to large chipping on the edges of the die. Stealth laser dicing achieves edge chipping of less than $2 mumathrm{m}$, which is the least amount of damage among of all dicing methods tested in this study. In the bonding test, the 10 mm square silicon die was bonded to a 35-mm square silicon substrate. Both silicon die and substrate are of thickness $760 mumathrm{m}$. Prior to direct oxide-oxide bonding, both silicon die, and substrate went through a two-step cleaning process. The detailed process of the plasma activated die-level direct bonding is discussed.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125484203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A New Semiconductor Package Design Flow and Platform Applied on High Density Fan-out Chip","authors":"Chen-Chao Wang, Chih-Yi Huang, K. Chang, Youle Lin","doi":"10.1109/ECTC32696.2021.00030","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00030","url":null,"abstract":"In recent years, because the needs of 5G mobile communications, artificial intelligence, self-driving cars, and high-speed networks product are highly increasing, more and more IC design companies have invested in a lots of computing and high-performance computing device development. At present, the package type used in such high-performance computing product mass production is 2.5D IC package with ultra-high density I/O, which is special for packaging of IC products such as AI, high performance GPU, and high-speed networking devices. Compared to the traditional Flip Chip BGA (FCBGA) package on the market, the 2.5D package has a unique silicon interposer, and there are ASIC chip and HBM chips on the silicon interposer. Between the ASIC chip and the HBM chips, a lot of high-speed signal lines and thousands of small vias are connected. In addition to the signal line between the ASIC chip and the HBM chip, the silicon interposer has an important structure-TSV (Through Silicon Via) to act as the connection between the ASIC chips or the HBM chips and the package substrate. Because of the existing of TSV, the production yield of the silicon interposer is not easy to increase. Considering productivity and cost, some OSAT (Outsourced Semiconductor Assembly and Test) companies hence [1]–[5] proposed some TSV-free packaging structures, such as FOCoS (Fan-out Chip on Substrate). According to different process, there are Chip First FOCoS and Chip last FOCoS, which are suitable for different applications and production costs [6]. The research and discussion in this paper, there are package design with the structure of FOCoS for an actual high-performance computing IC device with two ASIC chips. In the process of this actual project, the SiP-id (System-in-Package Intelligent Design) design platform was used to complete the routings of ultra-high density I/O such as the Si interposer MEOL (Middle End of Line) and Fan-Out RDL. Compared with the traditional design platform, it was greatly pull-in design cycle time. The design time and the accuracy of the design are improved obviously. In addition, this paper also delivers a lot of self-developed programs to link the design and validation tools from different vendors.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125591698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel integration scheme for wafer singulation and selective processing using temporary dry film resist","authors":"Alexandre La Grappe, Evert Visker, A. Redolfi, Lan Peng, Karthik Muga, David Huls, S. Vanhaelemeersch, A. Lauwers, J. Ackaert","doi":"10.1109/ECTC32696.2021.00136","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00136","url":null,"abstract":"Patterning on Si with high aspect ratio trenches by spin-coating of photoresist faces significant challenges. The desire to maintain a good thickness uniformity of resist on wafer surface, to minimize any residue inside deep trenches, as well as enabling low cost of ownership has led to new process techniques. Wafer level lamination using dry film resist (DFR) has emerged as a favorable option for such applications. In this paper, a unique application of temporary DFR to overcome deep Si trenches will be presented. The integration scheme offers novel possibilities for wafer singulation in addition to resolving the issues with conventional spin-coating. An example of this approach will be presented in detail. This unique integration flow can lead to new applications that would otherwise not be feasible in technological areas such as sensor, microfluidics and MEMS.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126755117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hybrid Bonding of Nanotwinned Copper/organic Dielectrics with Low Thermal Budget","authors":"K. Shie, Pin-Syuan He, Yu-Hao Kuo, J. Ong, K. Tu, B. Lin, Chia-Cheng Chang, Chih Chen","doi":"10.1109/ECTC32696.2021.00079","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00079","url":null,"abstract":"The temperature for hybrid bonding is favorably to be lower than 250 °C, and thus nanotwinned Cu (nt-Cu) and low curing temperature dielectrics were combined to achieve that. To facilitate the fabrication of highly (111)-oriented surface of nt-Cu, Cu first process was chosen. In contrast to damascene Cu process, Cu first process changed the sequences of dielectric coating and Cu electroplating processes. In this study, patterned nt-Cu was plated first, and then dielectric was added in the process before or after chemical mechanical planarization (CMP). Low-temperature polyimide (PI) and non-conductive paste (NCP) were used to conduct two kinds of processes of hybrid bonding. If PI was coated and partially cured on a patterned wafer before CMP, co-planarization of nt-Cu/PI should be done afterwards to fabricate Cu/PI structure. The Cu/PI hybrid bonding can be achieved at 200 °C for 30 min. If a patterned wafer was planarized firstly, NCP was dropped on the samples and bonding process can be carried out at 180 °C for 2 h. This process was denoted as Cu + NCP hybrid bonding. The above two methods of hybrid bonding could be achieved under 250 °C, and might be the solutions for hybrid bonding technology with low thermal budget.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123353200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability of Printed Microwave Electronics","authors":"S. Neermann, J. Franke, M. Sippel, K. Lomakin, G. Gold","doi":"10.1109/ECTC32696.2021.00283","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00283","url":null,"abstract":"In recent years, the focus of research and industry in the field of printed electronics has been primarily on challenges relating to process improvements like resolution and process stability or material improvements. In contrast, environmental simulation on-tests such as temperature shock tests or humidity-heat tests and their effects on electrical and mechanical properties as well as the high frequency (HF) properties of printed structures have hardly been considered so far. However, such environmental requirements for electronic components are particularly important for reliable use in all areas of printed electronics. In this paper, environmental simulation tests on printed conductive structures were therefore carried out and their effects on the electrical conductivity and microwave frequency properties were measured, analyzed and evaluated. The common environmental simulation test methods as well as their purpose and implementation variants are examined in detail for this purpose. Based on these fundamentals, first of all the selected substrate material RO4350B is printed with a conductive silver paste according to microwave frequency technical specifications using a dispensing printing process and sintered according to the manufacturers specifications. The substrate material has a relative permittivity $varepsilon_{r}=3.48$ on which the geometry of the additively produced structures depends. To achieve the required characteristic impedance $Z_{L}approx 50 Omega$, a width of $1080 mumathrm{m}$ must be reached. The printed samples are then subjected to various environmental simulation tests and examined using various measurement procedures. For the long-term reliability tests, the temperature shock test between −40°C and 140 °C for 1000 cycles, the humidity-heat test with 85°C and 85% relative humidity for 1000 h and the vibration test were selected according to DIN EN 60068. The evaluation methods are to focus on the effects of the environmental simulation tests on electrical and mechanical properties as well as the influence on the high-frequency properties. The conductivity is measured by means of four-wire measurement. A comparison was made of the electrical conductivity in the sintered state, during the reliability tests and at the end of the tests. The samples in the thermal shock test were examined after 250 cycles, 500 cycles, 750 cycles and 1000 cycles to make premature failures of the samples visible. In the moisture-heat test the samples were taken and examined after 500 h and 1000 h. The detection of defects and cracks is carried out using optical control. To determine the high-frequency characteristics, a 2-port measurement of the S-parameters up to 12 GHz was performed. The insertion loss without impact from the transitions was determined using a multi-line method. It can be summarized that the reliability tests have no significant influence on the insertion loss of the printed samples compared to the sintered references. While","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123056861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Flip chip interconnects based on carbon nanofibers-solder composites","authors":"E. Passalacqua, C. Laprais, M. Bylund, Q. Li, V. Marknäs, R. Andersson, A. Saleem, V. Desmaris","doi":"10.1109/ECTC32696.2021.00350","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00350","url":null,"abstract":"In this paper, we propose the introduction of vertically aligned carbon nanofibers (CNF) directly grown on the bonding pad by chemical vapor deposition at CMOS compatible temperatures as a solution to reinforce and confine the solder joint between two chips bonded by solder. This concept potentially enables the reduction of pitches and size of the solder interconnects. The solder joints are realized by thermal compression bonding technique and the assemblies are characterized by means of electrical measurements of daisy chains and kelvin structures formed by the connection of the two chips. Flip chip interconnects based on two solder composite solutions (CNFs/SnAg and CNFs/SAC305) are analyzed in terms of electrical resistance, and different growth conditions for the CNFs and a post-growth treatment have been tested. The addition of the carbon nanofibers to the solder led to an additional resistance lower than 10% of the total resistance, while possibly improving the reliability of the joint.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126299253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of Copper and Glass Interaction in Through Glass Via (TGV) During Thermal Cycling","authors":"K. Pan, Jiefeng Xu, Yang Lai, Seungbae Park, C. Okoro, Dhananjay Joshi, S. Pollard","doi":"10.1109/ECTC32696.2021.00263","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00263","url":null,"abstract":"Glass interposers have attracted much interest from academia and industry because of the outstanding material properties of glass. However, the thermal mismatch between a copper via and glass causes reliability issues, such as glass and TGV cracking, copper via protrusion, and copper via sliding and delamination. This study investigated the copper and glass (Corning® HPFS® Fused Silica) interaction in TGV during thermal cycling. Optical profilometry was used to measure the copper via protrusion during thermal cycling. The TGV was heated up from room temperature (RT) 23°C to 400°C and then cooled to RT. An irreversible copper protrusion height was recorded at different temperatures. Furthermore, in-plane deformation of the glass caused by thermal mismatch is another reliability concern. Thus, two-dimensional digital image correlation (2D DIC) was applied to measure the in-plane deformation of the HPFS glass near the TGV during thermal cycling. The TGV sample was heated to 400°C from RT by a hotplate, and then the sample was cooled to RT using liquid nitrogen. The in-plane displacement of HPFS glass reached its maximum around 250°C, then it started to decrease because of the copper protrusion and copper material change at elevated temperatures.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121110557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Flexible Power Module for Wearable Medical Devices with Wireless Recharging using Corrugated Flexible Coils","authors":"Guangqi Ouyang, G. Ezhilarasu, Henry Sun, Haoxiang Ren, Yu-Tao Yang, S. Iyer","doi":"10.1109/ECTC32696.2021.00355","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00355","url":null,"abstract":"In this work, flexible corrugated interconnection and Fan-Out Wafer-Level packaging platform called FlexTrate™ is used to fabricate a thin film, flexible, magnetic resonant wireless recharging module for charging commercial Li-ion battery at an output of 3.3 V constant voltage. A power management IC (LDO bare die LDBL20) for voltage regulation, a fullwave bridge rectifier, a Si-DT capacitor dies for antenna matching. The coil antenna is also fabricated on the PDMS substrate using standard BEOL Cu metallization. The designed power module can deliver 3.9 mW regulated power.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121226847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Feasibility Study of Nanotwinned Copper and Adhesive Hybrid Bonding for Heterogeneous Integration","authors":"C. Hsiao, H. Fu, C. Chiang, O. Lee, Tsung-Yu Ou Yang, Hsiang-Hung Chang","doi":"10.1109/ECTC32696.2021.00081","DOIUrl":"https://doi.org/10.1109/ECTC32696.2021.00081","url":null,"abstract":"In this study, the wafer-level nanotwinned copper (nt-Cu) and BCB adhesive hybrid bonding is proposed. The (111) oriented nt-Cu and BCB adhesive are used for electrical interconnection and mechanical enhancement, respectively. Nanotwinned copper direct bonding, BCB adhesive bonding, nt-Cu and BCB adhesive hybrid bonding are investigated. In nt-Cu direct bonding, the highly (111) oriented surface ratio of nt-Cu is 97% by increasing plating current density, the columnar grain size and (111) oriented surface ratio are identified by Focused Ion Beam (FIB) and Electron Back Scatter Diffraction (EBSD). The surface roughness of nt-Cu is reduced to 0.72 nm after Chemical Mechanical Polishing (CMP) and nt-Cu to nt-Cu direct bonding without large bonding voids is achieved at 250 °C for 1 h. In BCB adhesive bonding, BCB to BCB could be well bonded at 250 °C. There are no samples peeling after dicing and the average shear strength is larger than 24 MPa. Currently, the surface topography and bonding result of nt-Cu and BCB hybrid structure are improved after tuning BCB curing and fly cutting condition.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121488257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}