A novel integration scheme for wafer singulation and selective processing using temporary dry film resist

Abstract

Patterning on Si with high aspect ratio trenches by spin-coating of photoresist faces significant challenges. The desire to maintain a good thickness uniformity of resist on wafer surface, to minimize any residue inside deep trenches, as well as enabling low cost of ownership has led to new process techniques. Wafer level lamination using dry film resist (DFR) has emerged as a favorable option for such applications. In this paper, a unique application of temporary DFR to overcome deep Si trenches will be presented. The integration scheme offers novel possibilities for wafer singulation in addition to resolving the issues with conventional spin-coating. An example of this approach will be presented in detail. This unique integration flow can lead to new applications that would otherwise not be feasible in technological areas such as sensor, microfluidics and MEMS.