2019 IEEE International Test Conference in Asia (ITC-Asia)最新文献_第2页

Implementation of Parametric Hardware Trojan in FPGA 参数化硬件木马在FPGA中的实现

2019 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2019-09-01 DOI: 10.1109/ITC-Asia.2019.00020

Yipei Yang, Jing Ye, Xiaowei Li, Yinhe Han, Huawei Li, Yu Hu

引用次数: 0

Accurate and Fast Testing Technique of Operational Amplifier DC Offset Voltage in µV-Order by DC-AC Conversion 基于DC- ac转换的运算放大器直流偏置电压µv级精确快速测试技术

2019 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2019-09-01 DOI: 10.1109/ITC-Asia.2019.00014

Yuto Sasaki, K. Machida, Riho Aoki, Shogo Katayama, Takayuki Nakatani, Jianlong Wang, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, A. Kuwana, K. Hatayama, Haruo Kobayashi

引用次数: 7

Optimization of Cell-Aware ATPG Results by Manipulating Library Cells' Defect Detection Matrices 利用文库细胞缺陷检测矩阵优化细胞感知ATPG结果

2019 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2019-09-01 DOI: 10.1109/ITC-Asia.2019.00029

Zhan Gao, Min-Chun Hu, J. Swenton, Santosh Malagi, J. Huisken, K. Goossens, E. Marinissen

{"title":"Optimization of Cell-Aware ATPG Results by Manipulating Library Cells' Defect Detection Matrices","authors":"Zhan Gao, Min-Chun Hu, J. Swenton, Santosh Malagi, J. Huisken, K. Goossens, E. Marinissen","doi":"10.1109/ITC-Asia.2019.00029","DOIUrl":"https://doi.org/10.1109/ITC-Asia.2019.00029","url":null,"abstract":"Cell-aware test (CAT) explicitly targets defects inside library cells and therefore significantly reduces the number of test escapes compared to conventional automatic test pattern generation (ATPG) approaches that cover cell-internal defects only serendipitously. CAT consists of two steps, viz. (1) library characterization and (2) cell-aware ATPG. Defect detection matrices (DDMs) are used as the interface between both CAT steps; they record which cell-internal defects are detected by which cell-level test patterns. This paper proposes two algorithms that manipulate DDMs to optimize cell-aware ATPG results with respect to fault coverage, test pattern count, and compute time. Algorithm 1 identifies don't-care bits in cell patterns, such that the ATPG tool can exploit these during cell-to-chip expansion to increase fault coverage and reduce test-pattern count. Algorithm 2 selects, at cell level, a subset of preferential patterns that jointly provides maximal fault coverage at a minimized stimulus care-bit sum. To keep the ATPG compute time under control, we run cell-aware ATPG with the preferential patterns first, and a second ATPG run with the remaining patterns only if necessary. Selecting the preferential patterns maps onto a well-known N Phard problem, for which we derive an innovative heuristic that outperforms solutions in the literature. Experimental results on twelve circuits show average reductions of 43% of non-covered faults and 10% in chip-pattern count.","PeriodicalId":348469,"journal":{"name":"2019 IEEE International Test Conference in Asia (ITC-Asia)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130247336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Time-Related Hardware Trojan Attacks on Processor Cores 针对处理器核心的时间相关硬件木马攻击

2019 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2019-09-01 DOI: 10.1109/ITC-Asia.2019.00021

Man-Hsuan Kuo, Chun-Ming Hu, Kuen-Jong Lee

引用次数: 6

A Hybrid Embedded Multichannel Test Compression Architecture for Low-Pin Count Test Environments in Safety-Critical Systems 一种用于安全关键系统中低引脚数测试环境的混合嵌入式多通道测试压缩体系结构

2019 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2019-09-01 DOI: 10.1109/ITC-Asia.2019.00033

S. Huhn, Daniel Tille, R. Drechsler

{"title":"A Hybrid Embedded Multichannel Test Compression Architecture for Low-Pin Count Test Environments in Safety-Critical Systems","authors":"S. Huhn, Daniel Tille, R. Drechsler","doi":"10.1109/ITC-Asia.2019.00033","DOIUrl":"https://doi.org/10.1109/ITC-Asia.2019.00033","url":null,"abstract":"This work presents a novel hybrid compression architecture that seamlessly combines the advantages of an embedded test compression technique with a lightweight codewordbased compression scheme. Embedded test compression has proven to be beneficial and is widely used in industrial circuit designs. However, particularly, in test applications within lowpin-count environments, a certain number of test patterns is incompressible and will, therefore, be rejected. This leads to a test coverage decrease which, in turn, jeopardizes the zero defect policy of safety-critical applications like automotive microcontrollers. Therefore, the rejected test patterns are typically transferred in an uncompressed way bypassing the embedded compression, which is extremely costly. The proposed hybrid architecture mitigates the adverse impact of rejected test patterns on the compression ratio as well as on the test application time of state-of-theart techniques. The experimental evaluation of industrial-sized designs clearly shows that a significant compression ratio up to 67.4% and a test application time reduction up to 72.9% can be achieved when utilizing the existing multi-channel interfaces.","PeriodicalId":348469,"journal":{"name":"2019 IEEE International Test Conference in Asia (ITC-Asia)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131707467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

An Empirical Approach to RTL Scan Path Design Focusing on Structural Interpretation in Logic Synthesis 基于逻辑综合中结构解释的RTL扫描路径设计经验方法

2019 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2019-09-01 DOI: 10.1109/ITC-Asia.2019.00023

T. Iwagaki, Sho Yuasa, H. Ichihara, Tomoo Inoue

{"title":"An Empirical Approach to RTL Scan Path Design Focusing on Structural Interpretation in Logic Synthesis","authors":"T. Iwagaki, Sho Yuasa, H. Ichihara, Tomoo Inoue","doi":"10.1109/ITC-Asia.2019.00023","DOIUrl":"https://doi.org/10.1109/ITC-Asia.2019.00023","url":null,"abstract":"Register-transfer level (RTL) scan design aims at optimizing the scan logic as well as the original logic during logic synthesis by modifying a given RTL description to make every register scannable. The modified RTL description, however, is not uniquely determined for realizing the scan functionality, and therefore, one should carefully modify the description because different descriptions with the same functionality can yield different gate level (GL) circuits in terms of area/delay in practice. In this paper, RTL descriptions are presented for constructing intended scan paths that make use of existing RTL modules such as multiplexers (MUXs) and operational units to reduce the area overhead incurred by scan insertion. Such descriptions have been derived from preliminary experiments that extensively analyze the correspondence between a scan description, its structural interpretation in logic synthesis and the synthesized GL circuit. This paper also presents an algorithm for determining scan paths that maximally exploit effective RTL structures where existing MUXs can be utilized for scan path construction with low area overhead. Experimental results show that the proposed algorithm together with structure-aware scan descriptions is effective in reducing area overhead.","PeriodicalId":348469,"journal":{"name":"2019 IEEE International Test Conference in Asia (ITC-Asia)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123093865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Race and Glitch Handling: A Test Perspective 比赛和故障处理:测试视角

2019 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2019-09-01 DOI: 10.1109/ITC-Asia.2019.00028

Kun-Han Tsai

引用次数: 0

A Static Method for Analyzing Hotspot Distribution on the LSI 一种分析LSI上热点分布的静态方法

2019 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2019-09-01 DOI: 10.1109/ITC-Asia.2019.00026

K. Miyase, Yudai Kawano, Shyue-Kung Lu, X. Wen, S. Kajihara

引用次数: 0

Online Testing of Clock Delay Faults in a Clock Network 时钟网络中时钟延迟故障的在线测试

2019 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2019-09-01 DOI: 10.1109/ITC-Asia.2019.00041

Wei-Xiang Chu, Shi-Yu Huang

引用次数: 0

A Selection Method of Ring Oscillators for An On-Chip Digital Temperature And Voltage Sensor 片上数字温度电压传感器环形振荡器的选择方法

2019 IEEE International Test Conference in Asia (ITC-Asia) Pub Date : 2019-09-01 DOI: 10.1109/ITC-Asia.2019.00016

Yousuke Miyake, Yasuo Sato, S. Kajihara

引用次数: 3