Online Testing of Clock Delay Faults in a Clock Network

Abstract

Traditionally, it has been a difficult task to characterize the quality of a Clock Delay Fault (CDF). Here, a CDF is referred to a delay fault occurring in the clock network that causes an abnormal delay when a clock signal travels through it and thereby causing large-than-expected clock skews at the clock ports of some flip-flops. In a recent work [12], a modified flush test procedure taking short pulses as the test stimuli at selected clock cycles has been proven effective in characterizing a CDF. In this work, we extend this technique to support online Built-In Self-Test (BIST). We investigate two fault detection strategies, namely, valid-range criterion, and valid-span criterion, and we compare their fault detection abilities in terms of the minimum detectable CDF. With the proposed BIST scheme, the health condition of the clock network in a device operating in the field can be inspected on a regular basis so as to take precautions before the clock network breaks down due to deteriorating fault effects.