An Empirical Approach to RTL Scan Path Design Focusing on Structural Interpretation in Logic Synthesis

Abstract

Register-transfer level (RTL) scan design aims at optimizing the scan logic as well as the original logic during logic synthesis by modifying a given RTL description to make every register scannable. The modified RTL description, however, is not uniquely determined for realizing the scan functionality, and therefore, one should carefully modify the description because different descriptions with the same functionality can yield different gate level (GL) circuits in terms of area/delay in practice. In this paper, RTL descriptions are presented for constructing intended scan paths that make use of existing RTL modules such as multiplexers (MUXs) and operational units to reduce the area overhead incurred by scan insertion. Such descriptions have been derived from preliminary experiments that extensively analyze the correspondence between a scan description, its structural interpretation in logic synthesis and the synthesized GL circuit. This paper also presents an algorithm for determining scan paths that maximally exploit effective RTL structures where existing MUXs can be utilized for scan path construction with low area overhead. Experimental results show that the proposed algorithm together with structure-aware scan descriptions is effective in reducing area overhead.