2020 IEEE International Test Conference India最新文献_第2页

ITC India 2020 Table of Contents ITC印度2020目录

2020 IEEE International Test Conference India Pub Date : 2020-07-01 DOI: 10.1109/itcindia49857.2020.9171781

引用次数: 0

ITC India 2020 Keyword Index ITC印度2020关键词指数

2020 IEEE International Test Conference India Pub Date : 2020-07-01 DOI: 10.1109/itcindia49857.2020.9171787

引用次数: 0

Efficient Fault Detection and Diagnosis of Digital Microfluidic Biochip Using Multiple Electrodes Actuation 基于多电极驱动的数字微流控生物芯片故障检测与诊断

2020 IEEE International Test Conference India Pub Date : 2020-07-01 DOI: 10.1109/ITCIndia49857.2020.9171793

Sourav K. Ghosh, Dolan Maity, Arijit Chowdhury, S. Roy, C. Giri

引用次数: 1

An Efficient Hardware Trojan Detection Approach adopting Testability based Features 基于可测试性特征的硬件木马检测方法

2020 IEEE International Test Conference India Pub Date : 2020-07-01 DOI: 10.1109/ITCIndia49857.2020.9171786

M. Priyadharshini, P. Saravanan

引用次数: 4

Resource Optimal Realization of Fault-Tolerant Quantum Circuit 容错量子电路的资源优化实现

2020 IEEE International Test Conference India Pub Date : 2020-07-01 DOI: 10.1109/ITCIndia49857.2020.9171796

Abhoy Kole, I. Sengupta

{"title":"Resource Optimal Realization of Fault-Tolerant Quantum Circuit","authors":"Abhoy Kole, I. Sengupta","doi":"10.1109/ITCIndia49857.2020.9171796","DOIUrl":"https://doi.org/10.1109/ITCIndia49857.2020.9171796","url":null,"abstract":"Encoding of quantum information and carrying out computation on encoded state is an essential requirement for improving the reliability of a quantum computer. Resource limitation in today’s noisy intermediate scale quantum (NISQ) processors further restricts carrying out fault-tolerant quantum gate operations on such systems. Recent experiments conducted on physical qubits of superconducting transmon type and trapped atomic ions using the fault-tolerant scheme based on [[4, 2, 2]] code have shown a systematic improvement in the fidelity of all logical quantum gate operations except the logical controlled-NOT (CNOT) operation that requires 3 physical SWAP operations for fault-tolerant realization.In this present work we propose an optimal realization of logical CNOT operations on a single or two separate [[4, 2, 2]] code-words using 4 physical CNOT operations and an additional qubit. We further introduce logical two-qubit positive and negative controlled-phase operations with varying rotation angle, and also propose the fault-tolerant realization of logical 2-controlled-phase $(C^{2}Z)$ and 2-controlled-NOT (C2 NOT) operations that are required for universal computation using [[4, 2, 2]] encoding. The implementation requires less number of encoded operations and one additional qubit. Through experiments conducted on the 15-qubit IBM Quantum Experience processor and QASM simulator the fidelity and validity of all these proposed gate operations have been verified.","PeriodicalId":346727,"journal":{"name":"2020 IEEE International Test Conference India","volume":"64 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133117637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Critical Engineering Dissection of LOS and LOC At-speed Test Approaches LOS和LOC高速测试方法的关键工程剖析

2020 IEEE International Test Conference India Pub Date : 2020-07-01 DOI: 10.1109/ITCIndia49857.2020.9171794

K. Pandey

{"title":"A Critical Engineering Dissection of LOS and LOC At-speed Test Approaches","authors":"K. Pandey","doi":"10.1109/ITCIndia49857.2020.9171794","DOIUrl":"https://doi.org/10.1109/ITCIndia49857.2020.9171794","url":null,"abstract":"At-speed or delay fault models such as transition, small delay defects, and path delay require combination of two vectors to achieve delay fault excitation. The first vector is known as initialization vector $(mathrm{V}_{I})$ and second vector is known as transition launch $(mathrm{V}_{L})$ vector. The ability to find pair of VI and VL is very critical for transition launch and eventually for successful fault detection. The Launch Off Shift (LOS) and Launch Off Capture (LOC) are two widely deployed schemes for this purpose in test community. This paper performs in-depth analysis to understand strengths and weaknesses of LOS and LOC at-speed test approaches for industrial chips. The LOS scheme heavily relies on scan chain order to get desired $mathrm{V}_{I}-mathrm{V}_{L}$ pairs whereas LOC scheme heavily relies on functional design logic to get desired $mathrm{V}_{I}-mathrm{V}_{L}$ pairs. This analysis indicates a large number of delay faults can be detected by both LOS and LOC schemes. The interesting fact that has emerged is about 2% to 5% faults are uniquely detected by each scheme that cannot be detected by other scheme without adding test points. The LOC performance was much inferior to LOS performance around 15 years ago. But this has changed over the time and presently LOC outperforms LOS on important parameters like pattern count and test coverage. Moreover high implementation cost and large IR drop make LOS unviable for high speed (more than 1 GHz) designs.","PeriodicalId":346727,"journal":{"name":"2020 IEEE International Test Conference India","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123567448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Built-In Self-Repair for Manufacturing and Runtime TSV Defects in 3D ICs 3D集成电路制造和运行时TSV缺陷的内置自修复

2020 IEEE International Test Conference India Pub Date : 2020-07-01 DOI: 10.1109/ITCIndia49857.2020.9171797

D. K. Maity, S. Roy, C. Giri

引用次数: 5

Wavelet Transform based fault diagnosis in analog circuits with SVM classifier 基于小波变换的SVM分类器模拟电路故障诊断

2020 IEEE International Test Conference India Pub Date : 2020-07-01 DOI: 10.1109/ITCIndia49857.2020.9171798

S. Srimani, K. Ghosh, H. Rahaman

引用次数: 5

Machine Learning Driven Throughput Optimization of Volume Diagnosis Methodology 机器学习驱动的体积诊断方法的吞吐量优化

2020 IEEE International Test Conference India Pub Date : 2020-07-01 DOI: 10.1109/ITCIndia49857.2020.9171800

Sameer Chillarige, Anil Malik, M. Amodeo, Atul Chabbra, Bharath Nandakumar, Robert Redburn, Nicholai L’ Esperance, Jeff Zimmerman, Adisun Wheelock

{"title":"Machine Learning Driven Throughput Optimization of Volume Diagnosis Methodology","authors":"Sameer Chillarige, Anil Malik, M. Amodeo, Atul Chabbra, Bharath Nandakumar, Robert Redburn, Nicholai L’ Esperance, Jeff Zimmerman, Adisun Wheelock","doi":"10.1109/ITCIndia49857.2020.9171800","DOIUrl":"https://doi.org/10.1109/ITCIndia49857.2020.9171800","url":null,"abstract":"Numerous areas of VLSI Design and Automation including test and diagnosis have already started benefiting from machine learning based approaches. In this paper, we focus on application of machine learning techniques in the context of Volume Diagnosis methodology which aims at improving the yield analysis and management process. Specifically, we apply machine learning to monitor and predict throughput bottlenecks in diagnosis process that impede the pace of yield analysis. In the proposed supervised machine learning technique, diagnosis features extracted from thousands of devices are used to train a random forest regression model and features causing greatest impact on run times are predicted. This technique has resulted in identifying a class of faults (labelled “hyperactive faults”) to be strongly correlated to diagnosis run time. Based on this finding, we propose improvements to volume diagnosis methodology to identify and mask hyperactive faults in advance from volume diagnosis process. Experimental results using proposed improvements on large industrial designs demonstrate up to ~8% reduction in volume diagnosis run time with no loss of accuracy and resolution.","PeriodicalId":346727,"journal":{"name":"2020 IEEE International Test Conference India","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131923255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Modeling and Test Generation for Combinational Hardware Trojans 组合硬件木马的建模与测试生成

2020 IEEE International Test Conference India Pub Date : 2020-07-01 DOI: 10.1109/ITCIndia49857.2020.9171791

Manisha Vinta, S. Sivanantham

引用次数: 1