3D集成电路制造和运行时TSV缺陷的内置自修复

D. K. Maity, S. Roy, C. Giri
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引用次数: 5

摘要

与2DIC相比,基于硅通孔(tsv)的三维集成电路(3DIC)在导线长度、功耗、异构集成等方面具有多种优势。然而,由于制造工艺的原因,tsv中的缺陷降低了3DIC的可靠性。已经提出了几种最先进的方法来克服这些缺陷。然而,由于电迁移(EM), tsv在现场操作中可能会发生故障,这成为3dic的主要可靠性问题。因此,在出现电磁故障时,检测和修复至关重要。提出了一种运行时动态内置自修复(BISR)方法来提高运行时可靠性。BISR包括一个精确定位运行时缺陷和制造缺陷的测试方案,以及一个用相邻的无故障tsv替换有缺陷tsv的修复方案。实验结果表明,该方法在测试时间和面积开销方面显著降低了总体成本。对于0.5 ns的关键路径延迟,修复方案的延迟开销是合理的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Built-In Self-Repair for Manufacturing and Runtime TSV Defects in 3D ICs
Three-dimensional Integrated Circuit (3DIC) based on Through Silicon Vias (TSVs) has various benefits of wire length, power consumption, heterogeneous integration as compared to 2DIC. However, defects in TSVs due to manufacturing processes reduce the reliability of the 3DIC. Several state-of-art approaches have proposed to overcome these defects. However, TSVs can be failed during field operation due to Electromigration (EM), which becomes a major reliability concern in 3DICs. Therefore, detection and repair are crucial in the presence of EM failures. This paper presents a runtime dynamic Built-In Self-Repair (BISR) approach to enhance runtime reliability. BISR consists of a test scheme to pinpoint runtime defects as well as manufacturing defects and a repair scheme that replace defective TSVs with neighbor fault-free TSVs. Experimental results demonstrate that the proposed method reduces the overall cost in terms of test time and area overhead significantly. The delay overhead of the repair solution is reasonable for 0.5 ns critical path latency.
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