An Efficient Hardware Trojan Detection Approach adopting Testability based Features

Abstract

Insertion of Hardware Trojan (HT) by adversaries is a major security concern and detection of HT continues to stay as a topic of research. In a typical VLSI design flow, design and fabrication phases are the highly prone stages for HT insertion. The proposed work makes use of testability measures for HT detection since most of the trojan nets are governed by their testability measures. This approach experiments Knearest neighbor and SVM-based machine learning algorithms with SANDIA Controllability Observability Analysis Program (SCOAP) parameters, COP (Controllability/Observability Program) parameters and circuit size as the key features for training and classification. The proposed method is able to achieve 100% TPR (True positive rate) and TNR (True negative rate) values in various Trust-HUB combinational benchmark circuits and outperforms the existing methods in literature.