A Critical Engineering Dissection of LOS and LOC At-speed Test Approaches

Abstract

At-speed or delay fault models such as transition, small delay defects, and path delay require combination of two vectors to achieve delay fault excitation. The first vector is known as initialization vector $(\mathrm{V}_{I})$ and second vector is known as transition launch $(\mathrm{V}_{L})$ vector. The ability to find pair of VI and VL is very critical for transition launch and eventually for successful fault detection. The Launch Off Shift (LOS) and Launch Off Capture (LOC) are two widely deployed schemes for this purpose in test community. This paper performs in-depth analysis to understand strengths and weaknesses of LOS and LOC at-speed test approaches for industrial chips. The LOS scheme heavily relies on scan chain order to get desired $\mathrm{V}_{I}-\mathrm{V}_{L}$ pairs whereas LOC scheme heavily relies on functional design logic to get desired $\mathrm{V}_{I}-\mathrm{V}_{L}$ pairs. This analysis indicates a large number of delay faults can be detected by both LOS and LOC schemes. The interesting fact that has emerged is about 2% to 5% faults are uniquely detected by each scheme that cannot be detected by other scheme without adding test points. The LOC performance was much inferior to LOS performance around 15 years ago. But this has changed over the time and presently LOC outperforms LOS on important parameters like pattern count and test coverage. Moreover high implementation cost and large IR drop make LOS unviable for high speed (more than 1 GHz) designs.