Modeling and Test Generation for Combinational Hardware Trojans

Abstract

Because of globalization in the semiconductor industry and manufacturing processes, integrated circuits are more exposed to harmful attacks called hardware Trojan. This can be considered as a serious threat to the Integrated circuits. Due to the inclusion of hardware Trojan into the existing circuit, it causes the possible effects like changing the functionality of the circuit and discharges some-secret information to the attacker. In this paper, we designed a hardware Trojan, which consists of two parts namely Trigger used to activate Trojan and payload, which changes the functionality of the chip normally the payload is an XOR gate. 2K×(K-1) Trojans are generated for a one-line trigger merged with one payload line for a circuit with K signal lines. The Trojan is detected by generating test patterns by using standard ATPG Tools which detects conditional stuck-at faults-and allows us to find the Trojan coverage and in addition to that this model is effective in finding out the real Trojans.