发布求助
文献互助 智能选刊 最新文献

31st European Solid-State Device Research Conference最新文献

筛选
英文 中文
Design of 50nm MOSFETs with Biased Side-Gates 带有偏置边门的50nm mosfet的设计
31st European Solid-State Device Research Conference Pub Date : 2001-09-11 DOI: 10.1109/ESSDERC.2001.195257
B. Choi, W. Choi, Y. Choi, J. Lee, Byung-Gook Park
{"title":"Design of 50nm MOSFETs with Biased Side-Gates","authors":"B. Choi, W. Choi, Y. Choi, J. Lee, Byung-Gook Park","doi":"10.1109/ESSDERC.2001.195257","DOIUrl":"https://doi.org/10.1109/ESSDERC.2001.195257","url":null,"abstract":"","PeriodicalId":345274,"journal":{"name":"31st European Solid-State Device Research Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121832967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Junction leakage in advanced CMOS technologies 先进CMOS技术中的结漏
31st European Solid-State Device Research Conference Pub Date : 2001-09-11 DOI: 10.1109/ESSDERC.2001.195229
C. Dachs, R. Surdeanu, D. Guyot, A. Parlangeli, Y. Ponomarev, P. Stolk
{"title":"Junction leakage in advanced CMOS technologies","authors":"C. Dachs, R. Surdeanu, D. Guyot, A. Parlangeli, Y. Ponomarev, P. Stolk","doi":"10.1109/ESSDERC.2001.195229","DOIUrl":"https://doi.org/10.1109/ESSDERC.2001.195229","url":null,"abstract":"","PeriodicalId":345274,"journal":{"name":"31st European Solid-State Device Research Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116131936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Double-Gate MOSFETs: Is Gate Alignment Mandatory? 双栅mosfet:栅对齐是强制性的吗?
31st European Solid-State Device Research Conference Pub Date : 2001-09-11 DOI: 10.1109/ESSDERC.2001.195252
F. Allibert, A. Zaslavsky, J. Pretet, S. Cristoloveanu
{"title":"Double-Gate MOSFETs: Is Gate Alignment Mandatory?","authors":"F. Allibert, A. Zaslavsky, J. Pretet, S. Cristoloveanu","doi":"10.1109/ESSDERC.2001.195252","DOIUrl":"https://doi.org/10.1109/ESSDERC.2001.195252","url":null,"abstract":"Double-gate (DG) MOSFETs promise to enhance transistor capabilities beyond the limits of conventional CMOS technology. In this paper, we study for the first time the impact of gate misalignment in “non-ideal” DG devices that may be much easier to fabricate than self-aligned versions. Drain current, transconductance, series resistance effects, subthreshold slope and carrier concentration profiles are simulated for different architectures, based on a 50nm long SOI MOSFET. We compare single gate, ideal aligned DG, and non-aligned DG transistors in which unequal gate lengths are used to compensate for the gate misalignment. We find that non-aligned DG devices are competitive with and even, in some cases, superior to ideal DG MOS, albeit with unusual gm curves.","PeriodicalId":345274,"journal":{"name":"31st European Solid-State Device Research Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122295923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A Geiger Mode Avalanche Photodiode Fabricated in a Conventional CMOS Technology 用传统CMOS工艺制备盖革模式雪崩光电二极管
31st European Solid-State Device Research Conference Pub Date : 2001-09-11 DOI: 10.1109/ESSDERC.2001.195306
A. Rochas, P. Besse, R. Popovic
{"title":"A Geiger Mode Avalanche Photodiode Fabricated in a Conventional CMOS Technology","authors":"A. Rochas, P. Besse, R. Popovic","doi":"10.1109/ESSDERC.2001.195306","DOIUrl":"https://doi.org/10.1109/ESSDERC.2001.195306","url":null,"abstract":"A Geiger mode avalanche photodiode with outstanding characteristics is fully fabricated in a conventional CMOS process. The 80μm2 active area photodiode for blue detection contains an efficient guard-ring structure to prevent edge breakdown. The selectivity for blue is obtained using a P+/ Nwell/Psubstrate dual junction structure. The first junction close to the surface is biased above the breakdown voltage, the second junction is short-circuited. A characterization using a passive quenching method is done. A value of the dark count rate of only 220 c.p.s. is obtained for an excess bias voltage of -2.85V, at room temperature. The maximum Geiger mode quantum efficiency for this excess bias voltage is about 20% at λ=460nm. The fabrication in a CMOS process opens the way to the co-integration of passive quenching or active quenching depending on applications and read-out electronics.","PeriodicalId":345274,"journal":{"name":"31st European Solid-State Device Research Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122731906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
70 nm Damascene-Gate MOSFETs with Minimal Polysilicon Gate-Depletion 具有最小多晶硅栅极损耗的70纳米大马士革栅极mosfet
31st European Solid-State Device Research Conference Pub Date : 2001-09-11 DOI: 10.1109/ESSDERC.2001.195221
H. Hanafi, R. Arndt, D. Boyd, W. Natzle, A. Ticknor
{"title":"70 nm Damascene-Gate MOSFETs with Minimal Polysilicon Gate-Depletion","authors":"H. Hanafi, R. Arndt, D. Boyd, W. Natzle, A. Ticknor","doi":"10.1109/ESSDERC.2001.195221","DOIUrl":"https://doi.org/10.1109/ESSDERC.2001.195221","url":null,"abstract":"In this work, for the first time, we present very high performance CMOS devices with 70 nm gate length and 2.2 nm Tinv effective gate oxide thickness fabricated using a damascene-gate process. Poly-Si gate electrodes are used with minimal poly depletion due to the de-coupling of the gate implantation from the source and drain implantation in the damascene-gate process. Saturation transconductance of 722 μS/μm for nMOSFETs and 354 μS/μm for pMOSFETS are achieved. ION for a 1.5 V supply is 0.9 mA/um for the nMOSFETs and 0.43 mA/um for the pMOSFETs with IOFF of both devices is 20 nA/um. The reduced junction capacitance and minimal poly-Si gate depletion in the damascene process resulted in a measured delay per stage of 8.6 ps for a 101-stage CMOS inverter ring oscillator at 1.5 V supply.","PeriodicalId":345274,"journal":{"name":"31st European Solid-State Device Research Conference","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121984440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Realization of Compact MOSFET Structure by Waffle-Layout 用格子布局实现紧凑的MOSFET结构
31st European Solid-State Device Research Conference Pub Date : 2001-09-11 DOI: 10.1109/ESSDERC.2001.195215
S. Lam, W. Ki, K. C. Kwok, M. Chan
{"title":"Realization of Compact MOSFET Structure by Waffle-Layout","authors":"S. Lam, W. Ki, K. C. Kwok, M. Chan","doi":"10.1109/ESSDERC.2001.195215","DOIUrl":"https://doi.org/10.1109/ESSDERC.2001.195215","url":null,"abstract":"","PeriodicalId":345274,"journal":{"name":"31st European Solid-State Device Research Conference","volume":"77 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128663113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Pockets and offset spacer engineering for 100 nm CMOS 100纳米CMOS的口袋和偏移间隔器工程
31st European Solid-State Device Research Conference Pub Date : 2001-09-11 DOI: 10.1109/ESSDERC.2001.195293
R. Surdeanu, C. Dachs, P. Stolk, F. Cubaynes, Y. Ponomarev
{"title":"Pockets and offset spacer engineering for 100 nm CMOS","authors":"R. Surdeanu, C. Dachs, P. Stolk, F. Cubaynes, Y. Ponomarev","doi":"10.1109/ESSDERC.2001.195293","DOIUrl":"https://doi.org/10.1109/ESSDERC.2001.195293","url":null,"abstract":"In this paper we present a method for fabricating pockets suitable for 100 nm CMOS technology. 2D process and device simulations were performed to assess problems related to the optimisation of the source/drain extensions and pockets. Based on these results prototype devices were designed and processed in a 100 nm CMOS technology. The results demonstrate that sharp-profile pockets combined with spacers to offset the extensions implants result in very good device performance for PMOST. The main advantage of this approach is that it allows further downscaling of transistor’s gate length while limiting the short-channel effects.","PeriodicalId":345274,"journal":{"name":"31st European Solid-State Device Research Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129271099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 50nm channel vertical MOSFET concept incorporating a retrograde channel and a dielectric pocket 50nm沟道垂直MOSFET概念，包含逆行沟道和介电袋
31st European Solid-State Device Research Conference Pub Date : 2001-09-11 DOI: 10.1109/ESSDERC.2001.195272
A. Lamb, L. Riley, S. Hall, V. D. Kunz, C. D. de Groot, P. Ashburn
{"title":"A 50nm channel vertical MOSFET concept incorporating a retrograde channel and a dielectric pocket","authors":"A. Lamb, L. Riley, S. Hall, V. D. Kunz, C. D. de Groot, P. Ashburn","doi":"10.1109/ESSDERC.2001.195272","DOIUrl":"https://doi.org/10.1109/ESSDERC.2001.195272","url":null,"abstract":"A novel architecture for a vertical MOSFET is proposed and initial investigations conducted by numerical simulation.","PeriodicalId":345274,"journal":{"name":"31st European Solid-State Device Research Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123984100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Bulk and contact 1/f noise in GaN TLM structures GaN TLM结构中的体积和接触1/f噪声
31st European Solid-State Device Research Conference Pub Date : 2001-09-11 DOI: 10.1109/ESSDERC.2001.195274
R. Feyaerts, L. Vandamme, G. Trefán, M.C.J.C.M. Kramer, C. Zellweger
{"title":"Bulk and contact 1/f noise in GaN TLM structures","authors":"R. Feyaerts, L. Vandamme, G. Trefán, M.C.J.C.M. Kramer, C. Zellweger","doi":"10.1109/ESSDERC.2001.195274","DOIUrl":"https://doi.org/10.1109/ESSDERC.2001.195274","url":null,"abstract":"We measure the contact resistance and 1/f noise on n-type GaN samples grown by various vapour phase epitaxy (VPE) technologies. Contacts are made in a linear transmission line geometry (TLM). In some samples the metal semiconductor contact noise dominates. This 1/f noise spans over 4 decades. In other samples the bulk noise dominates. This 1/f noise is described by the empirical relation","PeriodicalId":345274,"journal":{"name":"31st European Solid-State Device Research Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124186260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Junction-to-Case Thermal Modeling and the Significance of the Junction Power Profile on Thermal Response 结-壳热建模及结功率分布对热响应的意义
31st European Solid-State Device Research Conference Pub Date : 2001-09-11 DOI: 10.1109/ESSDERC.2001.195310
E. McShane, K. Shenai
{"title":"Junction-to-Case Thermal Modeling and the Significance of the Junction Power Profile on Thermal Response","authors":"E. McShane, K. Shenai","doi":"10.1109/ESSDERC.2001.195310","DOIUrl":"https://doi.org/10.1109/ESSDERC.2001.195310","url":null,"abstract":"Transistor thermal models for ideal steady-state switching conditions have been studied thoroughly by others. Little has been reported, though, of modeling for abrupt fault-type conditions. We investigate two common assumptions made by steadystate models and demonstrate they are invalid for fault conditions. It is shown that broad matching of datasheet transient thermal impedance cannot be obtained with a single R-C equivalent circuit. More significantly, it is shown that the model of transient power dissipation has a pronounced impact on temperature profile. This issue is studied in unclamped inductive switching, where peak temperature and thermal gradient are affected. The result is critical for studying transistor reliability in fault conditions.","PeriodicalId":345274,"journal":{"name":"31st European Solid-State Device Research Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114802965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信